dsp56362 Freescale Semiconductor, Inc, dsp56362 Datasheet - Page 79

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dsp56362

Manufacturer Part Number
dsp56362
Description
Dsp56362 24-bit Audio Digital Signal Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale Semiconductor
144
146
147
148
149
150
151
152
153
154
157
158
No.
Serial clock rise/fall time
SS assertion to first SCK edge CPHA = 0
CPHA = 1
Last SCK edge to SS not asserted
Data input valid to SCK edge (data input
set-up time)
SCK last sampling edge to data input not
valid
SS assertion to data out active
SS deassertion to data high impedance
SCK edge to data out valid (data out delay
time)
SCK edge to data out not valid
(data out hold time)
SS assertion to data out valid (CPHA = 0)
First SCK sampling edge to HREQ output
deassertion
Last SCK sampling edge to HREQ output
not deasserted (CPHA = 1)
Characteristics
Table 3-21 Serial Host Interface SPI Protocol Timing (continued)
DSP56362 Technical Data, Rev. 4
Master/
Master/
Master/
Master/
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
slave
Filter Mode
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Narrow
Narrow
Narrow
Narrow
Narrow
Narrow
Narrow
Narrow
Narrow
Wide
Wide
Wide
Wide
Wide
Wide
Wide
Wide
Wide
MAX{(20-T
MAX{(40-T
Serial Host Interface SPI Protocol Timing
2.5×T
2.5×T
2.5×T
Expression
3.5×T
2.5×T
2.5×T
2.5×T
2.5×T
2.5×T
2.5×T
2×T
2×T
2×T
T
T
T
T
C
102
189
C
C
10
12
C
C
C
+106
0
0
0
0
0
2
9
C
+55
+33
C
C
C
+123
+210
+5
C
C
C
C
C
C
C
+33
+120
+217
+136
+15
+10
+30
+50
+30
+30
+80
C
C
), 0}
), 0}
Min
102
189
116
105
161
50
10
12
10
30
35
55
75
15
65
55
0
0
0
0
0
2
100MHz
2000
Max
143
230
145
242
10
53
43
55
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-53

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