dsp56362 Freescale Semiconductor, Inc, dsp56362 Datasheet - Page 15

• Manufacturer Part Number: dsp56362
• Description: Dsp56362 24-bit Audio Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

2.7
The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The
HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard
microcomputers, microprocessors, DSPs, and DMA hardware.
2.7.1
Signal functions associated with the HDI08 vary according to the interface operating mode as determined
by the HDI08 port control register (HPCR). See 6.5.6 Host Port Control Register (HPCR) on
page Section 6-13 for detailed descriptions of this register and (See Host Interface (HDI08) on
page Section 6-1.) for descriptions of the other HDI08 configuration registers.
Freescale Semiconductor
Signal Name
MODD/IRQD
RESET
Host Interface (HDI08)
Host Port Configuration
Type
Input
Input
State during Reset
Table 2-8 Interrupt and Mode Control (continued)
Input
Input
DSP56362 Technical Data, Rev. 4
Mode Select D/External Interrupt Request D—MODD/IRQD is an
active-low Schmitt-trigger input, internally synchronized to the DSP clock.
MODD/IRQD selects the initial chip operating mode during hardware reset
and becomes a level-sensitive or negative-edge-triggered, maskable
interrupt request input during normal instruction processing. MODA,
MODB, MODC, and MODD select one of 16 initial chip operating modes,
latched into OMR when the RESET signal is deasserted. If IRQD is
asserted synchronous to CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and asserting IRQD to exit the
wait state.
This input is 5 V tolerant.
Reset—RESET is an active-low, Schmitt-trigger input. When asserted,
the chip is placed in the reset state and the internal phase generator is
reset. The Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. If RESET is deasserted
synchronous to CLKOUT, exact start-up timing is guaranteed, allowing
multiple processors to start synchronously and operate together in
“lock-step.” When the RESET signal is deasserted, the initial chip
operating mode is latched from the MODA, MODB, MODC, and MODD
inputs. The RESET signal must be asserted during power up. A stable
EXTAL signal must be supplied while RESET is being asserted.
This input is 5 V tolerant.
Signal Description
Host Interface (HDI08)
2-9