adsp-21462 Analog Devices, Inc., adsp-21462 Datasheet - Page 44

• Manufacturer Part Number: adsp-21462
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 40. S/PDIF Transmitter Input Data Timing
1
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
Table 41. Over Sampling Clock (TxCLK) Switching Characteristics
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Parameter
TxCLK Frequency for TxCLK = 384 × FS
TxCLK Frequency for TxCLK = 256 × FS
Frame Rate
AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SISFS
SIHFS
SISD
SIHD
SITXCLKW
SITXCLK
SISCLKW
SISCLK
Table
1
1
1
1
40. Input signals (SCLK, FS, SDATA) are routed to the
SAMPLE EDGE
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Transmit Clock Width
Transmit Clock Period
Clock Width
Clock Period
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
(SDATA)
(TXCLK)
(SCLK)
(FS)
Figure 32. S/PDIF Transmitter Input Timing
Rev. PrC | Page 44 of 62 | January 2009
t
SITXCLKW
t
SISCLKW
t
t
SISCLK
SISFS
t
SISD
t
SITXCLK
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min
TBD
TBD
TBD
Preliminary Technical Data
t
t
SIHFS
SIHD
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
MHz
kHz