adsp-21462 Analog Devices, Inc., adsp-21462 Datasheet - Page 39
adsp-21462
Manufacturer Part Number
adsp-21462
Description
Sharc Processor
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADSP-21462.pdf
(62 pages)
- Current page: 39 of 62
- Download datasheet (819Kb)
Preliminary Technical Data
Sample Rate Converter—Serial Input Port
The ASRC input signals (SCLK, FS, and SDATA) are routed
from the DAI_P20–1 pins using the SRU. Therefore, the timing
specifications provided in
pins.
Table 36. ASRC, Serial Input Port
1
Parameter
Timing Requirements
t
t
t
t
t
t
AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SRCSFS
SRCHFS
SRCSD
SRCHD
SRCCLKW
SRCCLK
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
Table 36
DAI_P20
DAI_P20
DAI_P20
(SDATA)
(SCLK)
(FS)
are valid at the DAI_P20–1
-
-
-
1
1
1
Figure 25. ASRC Serial Input Port Timing
Rev. PrC | Page 39 of 62 | January 2009
t
SRCCLKW
ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
t
SRCSFS
t
SRCSD
t
SAMPLE EDGE
SRCCLK
t
SRCHFS
t
SRCHD
Min
TBD
TBD
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
TBD
TBD
Unit
ns
ns
ns
ns
ns
ns
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