adsp-21992 Analog Devices, Inc., adsp-21992 Datasheet - Page 8

• Manufacturer Part Number: adsp-21992
• Description: Mixed Signal Dsp Controller With Can
• Manufacturer: Analog Devices, Inc.

ADSP-21992
SPI is a 3-wire interface consisting of 2 data pins (MOSI and
MISO), one clock pin (SCK), and a single slave select input
(SPISS) that is multiplexed with the PF0 Flag I/O line and seven
slave select outputs (SPISEL1 to SPISEL7) that are multiplexed
with the PF1 to PF7 flag I/O lines. The SPISS input is used to
select the ADSP-21992 as a slave to an external master. The
SPISEL1 to SPISEL7 outputs can be used by the ADSP-21992
(acting as a master) to select/enable up to seven external slaves
in a multidevice SPI configuration. In a multimaster or a multi-
device configuration, all MOSI pins are tied together, all MISO
pins are tied together, and all SCK pins are tied together.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on the serial data
line. The serial clock line synchronizes the shifting and sam-
pling of data on the serial data line.
In master mode, the DSP core performs the following sequence
to set up and initiate SPI transfers:
The SCK line generates the programmed clock pulses for simul-
taneously shifting data out on MOSI and shifting data in on
MISO. In DMA mode only, transfers continue until the SPI
DMA word count transitions from 1 to 0.
In slave mode, the DSP core performs the following sequence to
set up the SPI port to receive data from a master transmitter:
In DMA mode only, reception continues until the SPI DMA
word count transitions from 1 to 0. The DSP core could con-
tinue, by queuing up the next DMA descriptor.
• PF0 can be used as slave select input line.
• PF1–PF7 can be used as external slave select output.
• Enables and configures the SPI port operation (data size
• Selects the target SPI slave with the SPISELx output pin
• Defines one or more DMA descriptors in Page 0 of I/O
• Enables the SPI DMA engine and specifies transfer direc-
• In nonDMA mode only, reads or writes the SPI port
• Enables and configures the SPI slave port to match the
• Defines and generates a receive DMA descriptor in Page 0
• Enables the SPI DMA engine for a receive access (optional
• Starts receiving the data on the appropriate SCK edges after
and transfer format).
(reconfigured programmable flag pin).
memory space (optional in DMA mode only).
tion (optional in DMA mode only).
receive or transmit data buffer.
operation parameters set up on the master (data size and
transfer format) SPI transmitter.
of memory space to interrupt at the end of the data transfer
(optional in DMA mode only).
in DMA mode only).
receiving an SPI chip select on the SPISS input pin (recon-
figured programmable flag pin) from a master.
Rev. A | Page 8 of 60 | August 2007
The slave mode transmit operation is similar, except the DSP
core specifies the data buffer in memory space, generates and
relinquishes control of the transmit DMA descriptor, and
begins filling the SPI port data buffer. If the SPI controller is not
ready on time to transmit, it can transmit a “zero” word.
DSP SERIAL PORT (SPORT)
The ADSP-21992 incorporates a complete synchronous serial
port (SPORT) for serial and multiprocessor communications.
The SPORT supports the following features:
• Bidirectional: The SPORT has independent transmit and
• Double buffered: The SPORT section (both receive and
• Clocking: The SPORT can use an external serial clock or
• Word length: Each SPORT section supports serial data
• Framing: Each SPORT section (receive and transmit) can
• Companding in hardware: Each SPORT section can per-
• Direct memory access with single cycle overhead: Using the
• Interrupts: Each SPORT section (receive and transmit)
• Multichannel capability: The SPORT can receive and trans-
• DMA Buffer: Each SPORT channel (Tx and Rx) supports a
receive sections.
transmit) has a data register for transferring data words to
and from other parts of the processor and a register for
shifting data in or out. The double buffering provides addi-
tional time to service the SPORT.
generate its own in a wide range of frequencies down to
0 Hz.
word lengths from three to 16 bits that can be transferred
either MSB first or LSB first.
operate with or without frame synchronization signals for
each data-word; with internally generated or externally
generated frame signals; with active high or active low
frame signals; with either of two pulse widths and frame
signal timing.
form A law and μ law companding according to CCITT
recommendation G.711.
built-in DMA master, the SPORT can automatically receive
and/or transmit multiple memory buffers of data with an
overhead of only one DSP cycle per data-word. The on-
chip DSP, via a linked list of memory space resident DMA
descriptor blocks, can configure transfers between the
SPORT and memory space. This chained list can be
dynamically allocated and updated.
generates an interrupt upon completing a data-word trans-
fer, or after transferring an entire buffer or buffers if DMA
is used.
mit data selectively from channels of a serial bit stream that
is time division multiplexed into up to 128 channels. This is
especially useful for T1 interfaces or as a network commu-
nication scheme for multiple processors. The SPORTs also
support T1 and E1 carrier systems.
DMA buffer of up to eight 16-bit transfers.