adsp-21992 Analog Devices, Inc., adsp-21992 Datasheet - Page 37

• Manufacturer Part Number: adsp-21992
• Description: Mixed Signal Dsp Controller With Can
• Manufacturer: Analog Devices, Inc.

External Port Read Cycle Timing
Table 21
For additional information on the ACK signal, see the discus-
sion
Table 21. External Port Read Cycle Timing
1
2
3
t
These are timing parameters that are based on worst-case operating conditions.
W = (number of wait states specified in wait register)
EMICLK
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
AKW
RDA
ADA
SDA
SD
HRD
DRSAK
CSRS
ARS
RSCS
RW
RSA
RWR
on Page
is the external memory Interface clock period. t
and
1, 2
35.
Figure 11
ACK Strobe Pulse Width
Address Valid to Data Access Setup
Chip Select Asserted to Data Access Setup
Data Valid to RD Deasserted Setup
RD Deasserted to Data Invalid Hold
ACK Delay from XMS Low
Chip Select Asserted to RD Asserted Delay
Address Valid to RD Setup and Delay
RD Deasserted to Chip Select Deasserted Setup
RD Asserted to Data Access Setup
RD Strobe Pulse Width
RD Deasserted to Address Invalid Setup
RD Deasserted to WR, RD Asserted
describe external port read operations.
HCLK
t
EMICLK
is the peripheral clock period.
Rev. A | Page 37 of 60 | August 2007
.
Min
t
5
0
0.5t
0.5t
0.5t
t
0.5t
t
HCLK
EMICLK
HCLK
EMICLK
EMICLK
EMICLK
HCLK
–2 + W
– 2
– 3
– 3
– 2
3
Max
t
t
t
0.5t
EMICLK
EMICLK
EMICLK
EMICLK
– 5+W
+ W
+ W
– 1
3
3
ADSP-21992
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns