xcr3128 Xilinx Corp., xcr3128 Datasheet - Page 9

• Manufacturer Part Number: xcr3128
• Description: Xcr3128 128 Macrocell Cpld
• Manufacturer: Xilinx Corp.

XCR3128: 128 Macrocell CPLD
9
Table 5: Programming Specifications
Terminations
The CoolRunner XCR3128 CPLDs are TotalCMOS
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the linear
region of the CMOS input structures, which can increase
the power consumption of the device. The XCR3128
CPLDs have programmable on-chip pull-down resistors on
each I/O pin. These pull-downs are automatically activated
by the fitter software for all unused I/O pins. Note that an I/O
macrocell used as buried logic that does not have the I/O
pin used for input is considered to be unused, and the
pull-down resistors will be turned on. We recommend that
any unused I/O pins on the XCR3128 device be left uncon-
nected.
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10k
pull-up resistors. These pins can be directly connected to
V
tains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
When using the JTAG/ISP functions, it is also recom-
mended that 10k
pins associated with the four mandatory JTAG signals. Let-
DC Parameters
V
I
V
V
V
V
TDO_I
TDO_I
AC Parameters
f
PWE
PWP
PWV
INIT
TMS_SU
TDI_SU
TMS_H
TDI_H
TDO_CO TDO valid after TCK
CCP
MAX
CC
Symbol
CCP
IH
IL
SOL
SOH
or GND, but using the external pull-up resistors main-
OL
OH
V
I
Input voltage (High)
Input voltage (Low)
Output voltage (Low)
Output voltage (High)
Output current (Low)
Output current (High)
CLK maximum frequency
Pulse width erase
Pulse width program
Pulse width verify
Initialization time
TMS setup time before TCK
TDI setup time before TCK
TMS hold time after TCK
TDI hold time after TCK
CC
CC
limit program/verify
supply program/verify
pull-up resistors be used on each of the
Parameter
www.xilinx.com
1-800-255-7778
ting these signals float can cause the voltage on TMS to
come close to ground, which could cause the device to
enter JTAG/ISP mode at unspecified times. See the appli-
cation notes JTAG and ISP Overview for Xilinx XPLA1 and
XPLA2 CPLDs and Terminating Unused I/O Pins in Xilinx
XPLA1 and XPLA2 CoolRunner CPLDs for more informa-
tion.
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD’s and other integrated cir-
cuits. The Xilinx XCR3128 supports the following methods:
• PC parallel port
• Workstation or PC serial port
• Embedded processor
• Automated test equipment
• Third party programmers
• High-End JTAG and ISP tools
A Boundary-Scan Description Language (BSDL) descrip-
tion of the XCR3128 is also available from Xilinx for use in
test program development. For more details on JTAG and
ISP for the XCR3128, refer to the related application note:
JTAG and ISP Overview for Xilinx XPLA1 and XPLA2
CPLDs.
Min.
100
100
3.0
DS034 (v1.2) August 10, 2000
2.0
2.4
10
10
10
10
10
25
25
-8
8
Max.
200
3.6
0.8
0.5
40
MHz
Unit
mA
mA
mA
ms
ms
ns
ns
ns
ns
ns
V
V
V
V
V
s
s
R