xcr3128 Xilinx Corp., xcr3128 Datasheet - Page 2

• Manufacturer Part Number: xcr3128
• Description: Xcr3128 128 Macrocell Cpld
• Manufacturer: Xilinx Corp.

The XCR3128 CPLD is electrically reprogrammable using
industry standard device programmers from vendors such
as Data I/O, BP Microsystems, SMS, and others. The
XCR3128 also includes an industry-standard, IEEE
1149.1, JTAG interface through which in-system program-
ming (ISP) and reprogramming of the device is supported.
XPLA Architecture
Figure 1
cell device implementing the XPLA architecture. The XPLA
architecture consists of logic blocks that are interconnected
Figure 1: Xilinx XPLA Architecture
DS034 (v1.2) August 10, 2000
shows a high level block diagram of a 128 macro-
R
I/O
I/O
I/O
I/O
MC15
MC15
MC15
MC15
MC0
MC1
MC0
MC1
MC0
MC1
MC0
MC1
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
36
16
16
36
16
16
36
16
16
36
16
16
www.xilinx.com
1-800-255-7778
ZIA
by a Zero-power Interconnect Array (ZIA). The ZIA is a vir-
tual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macro-
cells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
36
16
16
36
16
16
36
16
16
36
16
16
BLOCK
BLOCK
BLOCK
BLOCK
XCR3128: 128 Macrocell CPLD
LOGIC
LOGIC
LOGIC
LOGIC
MC15
MC15
MC15
MC15
MC0
MC1
MC0
MC1
MC0
MC1
MC0
MC1
SP00464
I/O
I/O
I/O
I/O
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