epm2210gm100i Altera Corporation, epm2210gm100i Datasheet - Page 65

no-image

epm2210gm100i

Manufacturer Part Number
epm2210gm100i
Description
Section I. Max Ii Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
Figure 4–3. ESD Protection During Positive Voltage Zap
Altera Corporation
December 2007
I/O
When the I/O pin receives a negative ESD zap at the pin that is less than
–0.7 V (0.7 V is the voltage drop across a diode), the intrinsic
P-Substrate/N+ drain diode is forward biased. Therefore, the discharge
ESD current path is from GND to the I/O pin, as shown in
GND
Source
Drain
Drain
Source
NMOS
PMOS
Hot Socketing and Power-On Reset in MAX II Devices
Gate
Gate
P-Substrate
MAX II Device Handbook, Volume 1
N+
N+
D
S
GND
I/O
G
Figure
4–4.
4–5

Related parts for epm2210gm100i