epm2210gm100i Altera Corporation, epm2210gm100i Datasheet - Page 15

• Manufacturer Part Number: epm2210gm100i
• Description: Section I. Max Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 2–5. LAB-Wide Control Signals
Altera Corporation
March 2008
Dedicated
LAB Column
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
4
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal also uses labclkena1. If the
LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. Deasserting the clock enable signal turns off the
LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load /preset signal. By default, the Quartus II software uses a NOT gate
push-back technique to achieve preset. If you disable the NOT gate
push-back option or assign a given register to power-up high using the
Quartus II software, the preset is then achieved using the asynchronous
load signal with asynchronous load data input tied high.
With the LAB-wide addnsub control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as correlators and signed
multipliers that alternate between addition and subtraction depending
on data.
The LAB column clocks [3..0], driven by the global clock network, and
LAB local interconnect generate the LAB-wide control signals. The
MultiTrack interconnect structure drives the LAB local interconnect for
non-global control signal generation. The MultiTrack interconnect’s
inherent low skew allows clock and control signal distribution in addition
to data.
labclk1
Figure 2–5
labclkena1
labclk2
shows the LAB control signal generation circuit.
labclkena2
asyncload
or labpre
syncload
MAX II Device Handbook, Volume 1
labclr1
labclr2
MAX II Architecture
synclr
addnsub
2–7