dac1405d650 NXP Semiconductors, dac1405d650 Datasheet - Page 22

• Manufacturer Part Number: dac1405d650
• Description: Dual 14-bit Dac, Up To 650 Msps; 2? 4? And 8? Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1405D650_1
Product data sheet
In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode
frequency. Data enters the latch on the rising edge of the internal clock signal. The data is
sent to either latch I or latch Q, depending on the SELIQ signal.
The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and
Q channels; see
edge)”.
SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse)
signal. The first data following the SELIQ rising edge will be sent in channel I and following
data will be sent in channel Q. After this, data will be distributed alternately between these
channels.
Fig 6.
Fig 7.
(asynchronous alternative 1)
(asynchronous alternative 2)
Interleaved mode operation
Interleaved mode timing (8x interpolation, latch on rising edge)
(synchronous alternative)
I13 to I0
SELIQ
(Q13)
Figure 7 “Interleaved mode timing (8x interpolation, latch on rising
Latch Q output
Latch I output
14
I13 to I0
CLK
SELIQ
SELIQ
SELIQ
Rev. 01 — 4 May 2009
Dual 14-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
dig
LATCH
LATCH
Q
I
N
2
2
N + 1
FIR 1
FIR 1
XX
XX
N + 2
2
2
FIR 2
FIR 2
N + 3
N + 1
N
DAC1405D650
N + 4
2
2
FIR 3
FIR 3
© NXP B.V. 2009. All rights reserved.
001aaj586
N + 5
N + 2
N + 3
001aaj814
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