dac1405d650 NXP Semiconductors, dac1405d650 Datasheet - Page 14

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dac1405d650

Manufacturer Part Number
dac1405d650
Description
Dual 14-bit Dac, Up To 650 Msps; 2? 4? And 8? Interpolating
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
DAC1405D650_1
Product data sheet
Fig 3.
RESET_N
(optional)
(optional)
SCS_N
SCLK
SDIO
SDO
R/W indicates the mode access, (see
SPI protocol
10.2.2 SPI timing description
R/W
Table 6.
In
byte.
Table 7.
A[4:0]: indicates which register is being addressed. In the case of a multiple transfer, this
address concerns the first register after which the next registers follow directly in a
decreasing order according to
The SPI interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in
Figure
R/W
0
1
N1
0
0
1
1
N1
Table 7
N0
4.
below N1 and N0 indicate the number of bytes transferred after the instruction
Read or Write mode access description
Number of bytes to be transferred
A4
A3
Table
Description
Write mode operation
Read mode operation
N0
0
1
0
1
6):
A2
Rev. 01 — 4 May 2009
Dual 14-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
A1
Table 9 “Register allocation
A0
D7
D7
Number of bytes
1 byte transferred
2 bytes transferred
3 bytes transferred
4 bytes transferred
D6
D6
D5
D5
D4
D4
map”.
DAC1405D650
D3
D3
D2
D2
© NXP B.V. 2009. All rights reserved.
D1
D1
D0
D0
001aaj812
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