adv7718 Analog Devices, Inc., adv7718 Datasheet - Page 7
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adv7718
Manufacturer Part Number
adv7718
Description
Integrated Digital Ccir-601 Pal/ntsc Video Encoder
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADV7718.pdf
(40 pages)
3.3 V TIMING SPECIFICATIONS
Parameter
MPU PORT
ANALOG OUTPUTS
CLOCK CONTROL
AND PIXEL PORT
RESET CONTROL
INTERNAL CLOCK CONTROL
OSD TIMING
NOTES
1
2
3
4
5
6
Specifications subject to change without notice.
The max/min specifications are guaranteed over this range.
Temperature range T
TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
Guaranteed by characterization.
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
Clock Input:
SCLOCK Frequency
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t
Analog Output Delay
DAC Analog Output Skew
f
Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t
Digital Output Access Time, t
Digital Output Hold Time, t
Pipeline Delay, t
RESET Low Time
Clock/2 Rise Time, t
Clock/2 Fall Time, t
OSD Setup Time, t
OSD Hold Time, t
CLOCK
3, 4
4
P15–P0
HSYNC, FIELD/VSYNC, BLANK
CLOCK
MIN
15
3, 4, 6
3, 4
12
to T
10
19
5
11
9
18
17
3, 5
16
12
MAX
11
: 0°C to 70°C.
14
2
1
13
3
8
4
7
6
Conditions
After This Period the First Clock Is Generated
Repeated for Start Condition
(V
otherwise noted.)
AA
= 3.0 V–3.6 V
1
, V
REF
= 1.235 V, R
SET
= 300
Min
0
4.0
4.7
4.0
4.7
250
4.7
8
8
3.5
4
4
3
6
. All specifications T
Typ
7
0
27
4
37
10
10
10
2
ADV7177/ADV7178
Max
100
1
300
24
MIN
to T
MAX
Unit
kHz
µs
µs
µs
µs
ns
µs
ns
µs
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
ns
ns
ns
ns
2
unless