adv7718 Analog Devices, Inc., adv7718 Datasheet - Page 10

• Manufacturer Part Number: adv7718
• Description: Integrated Digital Ccir-601 Pal/ntsc Video Encoder
• Manufacturer: Analog Devices, Inc.

ADV7177/ADV7178
Pin Number
1, 20, 28, 30
2
3–10, 12–14,
37–41
11
15
16
17
18
19, 21, 29, 42
22
23
24
25
26
27
31
32
33
34–36
43
44
Mnemonic
V
CLOCK/2
P15–P0
OSD_EN
HSYNC
FIELD/VSYNC I/O
BLANK
ALSB
GND
RESET
SCLOCK
SDATA
COMP
DAC C
DAC B
DAC A
V
R
OSD_0–2
CLOCK
CLOCK
AA
REF
SET
Input/
Output
P
O
I
I
I/O
I/O
I
G
I
I
I/O
O
O
O
O
I/O
I
I
O
I
CLOCK/2
OSD_EN
P10
P12
V
P11
P5
P6
P7
P8
P9
AA
Function
Power Supply
Synchronous Clock output signal. Can be either 27 MHz or 13.5 MHz; this can be
controlled by MR32 and MR33 in Mode Register 3.
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb Pixel Port
Enables OSD input data on the video outputs.
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output
(Master Mode) or accept (Slave Mode) Sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may
be configured to output (Master Mode) or accept (Slave Mode) these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level
“0.” This signal is optional.
TTL Address Input. This signal sets up the LSB of the MPU address.
Ground Pin
The input resets the on-chip timing generator and sets the ADV7177/ADV7178 into
default mode. This is NTSC operation, Timing Slave Mode 0, 8-Bit Operation,
2 × Composite and S VHS out.
MPU Port Serial Interface Clock Input
MPU Port Serial Data Input/Output
Compensation Pin. Connect a 0.1 µF Capacitor from COMP to V
DAC C Analog Output
DAC B Analog Output
DAC A Analog Output
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 300 Ω resistor connected from this pin to GND is used to control full-scale amplitudes
of the Video Signals.
On Screen Display Inputs.
Crystal Oscillator output (to crystal). Leave unconnected if no crystal is used.
Crystal Oscillator input. If no crystal is used this pin can be driven by an external TTL
Clock source; it requires a stable 27 MHz reference Clock for standard operation.
Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square
pixel operation.
(P15–P0). P0 represents the LSB.
10
11
PIN FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
12 13 14 15 16 17 18 19 20 21 22
44
PIN 1
IDENTIFIER
PIN CONFIGURATION
43
42
ADV7177/ADV7178
41
(Not to Scale)
TOP VIEW
40 39 38
PQFP
37
36 35 34
33
32
31
30
29
28
27
26
25
24
23
R
V
GND
DAC A
V
V
DAC B
DAC C
COMP
SDATA
SCLOCK
SET
REF
AA
AA
AA
.