adv7718 Analog Devices, Inc., adv7718 Datasheet - Page 22

• Manufacturer Part Number: adv7718
• Description: Integrated Digital Ccir-601 Pal/ntsc Video Encoder
• Manufacturer: Analog Devices, Inc.

ADV7177/ADV7178
REGISTER ACCESSES
The MPU can write to or read from all of the ADV7177/ADV7178
registers except the subaddress register, which is a write-only regis-
ter. The subaddress register determines which register the next
read or write operation accesses. All communications with the part
through the bus start with an access to the subaddress register.
A read/write operation is performed from/to the target address,
which then increments to the next address until a stop command
on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NTSC pedestal
control registers in terms of its configuration.
Subaddress Register (SR7–SR0)
The communications register is an 8-bit write-only register. After
the part has been accessed over the bus, and a read/write operation is
selected, the subaddress is set up. The subaddress register deter-
mines to/from which register the operation takes place.
Figure 24 shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–SR6.
Register Select (SR5–SR0)
These bits are set up to point to the required starting address.
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
•
•
SR7
ZERO SHOULD BE WRITTEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
•
0
TO THESE BITS
SR7–SR6 (00)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
•
0
SR6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
•
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
•
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
•
1
SR5
ADV7178 SUBADDRESS REGISTER
MODE REGISTER 0
MODE REGISTER 1
SUBCARRIER FREQ REGISTER 0
SUBCARRIER FREQ REGISTER 1
SUBCARRIER FREQ REGISTER 2
SUBCARRIER FREQ REGISTER 3
SUBCARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 1
CLOSED CAPTIONING DATA – BYTE 0
CLOSED CAPTIONING DATA – BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
MODE REGISTER 3
MACROVISION REGISTER
MACROVISION REGISTER
"
"
SR4
"
"
SR3
SR2
SR1
MODE REGISTER 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)
Figure 25 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR01–MR00)
These bits are used to set up the encode mode. The ADV7177/
ADV7178 can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M) standard video.
Pedestal Control (MR02)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid if the ADV7177/
ADV7178 is configured in PAL mode.
Luminance Filter Control (MR04–MR03)
The luminance filters are divided into two sets (NTSC/PAL) of
four filters, low-pass A, low-pass B, notch and extended. When
PAL is selected, bits MR03 and MR04 select one of four PAL
luminance filters; likewise, when NTSC is selected, bits MR03 and
MR04 select one of four NTSC luminance filters. The filters are
illustrated in the Typical Performance Characteristics, TPCs 1–7.
RGB Sync (MR05)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
•
1
SR0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
•
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
•
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
•
1
ADV7177 SUBADDRESS REGISTER
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
•
0
MODE REGISTER 0
MODE REGISTER 1
SUBCARRIER FREQ REGISTER 0
SUBCARRIER FREQ REGISTER 1
SUBCARRIER FREQ REGISTER 2
SUBCARRIER FREQ REGISTER 3
SUBCARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 1
CLOSED CAPTIONING DATA – BYTE 0
CLOSED CAPTIONING DATA – BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
MODE REGISTER 3
OSD REGISTER
"
"
OSD REGISTER
"
"