pca9691 NXP Semiconductors, pca9691 Datasheet - Page 6

• Manufacturer Part Number: pca9691
• Description: 8-bit A/d And D/a Converter
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9691_1
Product data sheet
7.2 Control byte
Table 4.
The second byte sent to a PCA9691 is stored in its control register and is required to
control the PCA9691 function.
The upper nibble of the control register is used for enabling the analog output, and for
programming the analog inputs as single-ended or differential inputs. The lower nibble
selects one of the analog input channels defined by the upper nibble (see
If the auto-increment flag is set, the channel number is incremented automatically after
each A/D conversion.
If the auto-increment mode is selected and the internal oscillator is used, the analog
output enable flag in the control byte (bit 6) must be set. This allows the internal oscillator
to run continuously, thereby preventing conversion errors resulting from oscillator start-up
delay. The analog output enable flag can be reset at other times to reduce quiescent
power consumption.
The selection of a non-existing input channel results in the highest available channel
number being allocated. Therefore, if the auto-increment flag is set, the next selected
channel is always channel 0.
After power-on all bits of the control register are reset to logic 0. The DAC and the
oscillator are disabled for power saving. The analog output is switched to a
high-impedance state.
The most significant bits of both nibbles are reserved for oscillator control. Bit 7 and bit 3
can be set when the interface frequency is f
two bits to logic 1 sets the internal frequency to half and the accuracy of the A/D and D/A
conversion is 1 LSB as indicated in
The oscillator output is disabled in normal operation (pin OSC = LOW). Setting bit 7 to
logic 0 and bit 3 to logic 1 will enable this output in order to observe the oscillator
frequency (divided by 4).
Pin
A2
SCL
SCL
SDA
SDA
A1
SCL
SDA
SCL
SDA
PCA9691 address map
A0
SDA
SDA
SDA
SCL
Rev. 01 — 8 April 2008
Bit
A6
1
1
1
1
A5
0
0
0
0
…continued
A4
1
1
1
1
Table 8
A3
1
1
1
1
and
SCL
A2
1
1
1
1
Table
400 kHz (see
A1
0
0
1
1
9.
A0
0
1
0
1
8-bit A/D and D/A converter
Figure
R/W
0
0
0
0
PCA9691
5). Setting these
© NXP B.V. 2008. All rights reserved.
B8h
BAh
BCh
BEh
Address
Figure
5).
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61
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Nr