pca9691 NXP Semiconductors, pca9691 Datasheet - Page 18

• Manufacturer Part Number: pca9691
• Description: 8-bit A/d And D/a Converter
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 7.
V
V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
PCA9691_1
Product data sheet
Symbol Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
w(spike)
DD
DD
= 2.5 V to 5.5 V; V
(see
The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is
held LOW for a minimum of 25 ms. You must disable the bus time-out feature for DC operation.
t
t
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region of the SCL’s falling edge.
C
The maximum t
series protection resistors to be connected between the SDA pin and the SDA bus line and between the SCL pin and the SCL bus line
without exceeding the maximum t
Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
Figure
SCL clock frequency
bus free time
between a STOP
and START
condition
hold time (repeated)
START condition
set-up time for a
repeated START
condition
set-up time for STOP
condition
data hold time
data valid
acknowledge time
data valid time
data set-up time
LOW period of the
SCL clock
HIGH period of the
SCL clock
fall time of both SDA
and SCL signals
rise time of both
SDA and SCL
signals
spike pulse width
= minimum time for valid SDA (out) data following SCL LOW.
= time for acknowledgement signal from SCL LOW to SDA (out) LOW.
I
2
C-bus characteristics
10.2 Dynamic characteristics
22).
f
for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, t
SS
= 0 V; T
Conditions
amb
f
.
= 40 C to +85 C; reference to 30 % and 70 % with an input voltage swing of V
[4][5][6]
[4][5][6]
[1]
[2]
[3]
[7]
Rev. 01 — 8 April 2008
Standard mode
Min
300
250
4.7
4.0
4.7
4.0
0.1
4.7
4.0
0
0
-
-
-
1000
Max
3.45
100
300
50
-
-
-
-
-
-
-
-
-
20 + 0.1C
20 + 0.1C
Min
100
1.3
0.6
0.6
0.6
0.1
1.3
0.6
75
Fast mode
0
0
-
b
b
8-bit A/D and D/A converter
Max
400
300
300
0.9
50
-
-
-
-
-
-
-
-
-
IL
of the SCL signal) in order to
Fast-mode Plus Unit
f
0.26
0.26
0.26
0.05
0.26
is 250 ns. This allows
Min
0.5
0.5
75
50
PCA9691
0
0
-
-
-
© NXP B.V. 2008. All rights reserved.
1000
Max
0.45
450
120
120
50
-
-
-
-
-
-
-
-
18 of 28
SS
kHz
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
to