pca9575 NXP Semiconductors, pca9575 Datasheet - Page 14

• Manufacturer Part Number: pca9575
• Description: 16-bit I2c-bus And Smbus, Level Translating, Low Voltage Gpio With Reset And Interrupt
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9575_1
Product data sheet
7.6.7 Register 6 - Pull-up/pull-down select port 0 register
7.6.8 Register 7 - Pull-up/pull-down select port 1 register
When bus-hold feature is not selected and bit 1 of Register 4 is set to logic 1, the I/O
port 0 can be configured to have pull-up or pull-down by programming the
pull-up/pull-down register. Setting a bit to logic 1 will select a 100 k pull-up resistor for
that I/O pin. Setting a bit to logic 0 will select a 100 k pull-down resistor for that I/O pin. If
the bus-hold feature is enabled, writing to this register will have no effect on
pull-up/pull-down selection.
Table 10.
Legend: * default value.
When bus-hold feature is not selected and bit 1 of Register 5 is set to logic 1, the I/O
port 1 can be configured to have pull-up or pull-down by programming the
pull-up/pull-down register. Setting a bit to logic 1 will select a 100 k pull-up resistor for
that I/O pin. Setting a bit to logic 0 will select a 100 k pull-down resistor for that I/O pin. If
the bus-hold feature is enabled, writing to this register will have no effect on
pull-up/pull-down selection.
Table 11.
Legend: * default value.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Symbol
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Symbol
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Register 6 - Pull-up/pull-down select port 0 register (address 06h) bit description
Register 7 - Pull-up/pull-down select port 1 register (address 07h) bit description
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 01 — 2 October 2008
16-bit I
Value
1*
1*
1*
1*
1*
1*
1*
1*
Value
1*
1*
1*
1*
1*
1*
1*
1*
2
C-bus and SMBus, level translating, low voltage GPIO
Description
configures I/O port 0 pin to have pull-up or pull-down when
bus-hold feature not selected and bit 1 of Register 4 is logic 1
Description
configures I/O port 1 pin to have pull-up or pull-down when
bus-hold feature not selected and bit 1 of Register 5 is logic 1
0 = selects a 100 k pull-down resistor for that I/O pin
1 = selects a 100 k pull-up resistor for that I/O pin (default
value)
0 = selects a 100 k pull-down resistor for that I/O pin
1 = selects a 100 k pull-up resistor for that I/O pin (default
value)
PCA9575
© NXP B.V. 2008. All rights reserved.
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