pca9501 NXP Semiconductors, pca9501 Datasheet - Page 12

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pca9501

Manufacturer Part Number
pca9501
Description
8-bit I2c And Smbus I/o Port With Interrupt, 2-kbit Eeprom And 6 Address Pins
Manufacturer
NXP Semiconductors
Datasheet

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Acknowledge (see Figure 19)
The number of data bytes transferred between the start and the stop
conditions from transmitter to receiver is not limited. Each byte of
eight bits is followed by one acknowledge bit. The acknowledge bit
is a HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked
2004 Sep 30
8-bit I
2-kbit EEPROM and 6 address pins
2
C and SMBus I/O port with interrupt,
BY TRANSMITTER
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
START
CONDITION
S
Figure 19. Acknowledgment on the I
1
12
out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set-up and hold times must be
taken into account.
A master receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.
2
NOT ACKNOWLEDGE
2
C-bus
ACKNOWLEDGE
CLOCK PULSE FOR
ACKNOWLEDGEMENT
8
9
PCA9501
Product data sheet
SW00545

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