pca9501 NXP Semiconductors, pca9501 Datasheet - Page 10

• Manufacturer Part Number: pca9501
• Description: 8-bit I2c And Smbus I/o Port With Interrupt, 2-kbit Eeprom And 6 Address Pins
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Read operations
PCA9501 read operations are initiated in an identical manner to
write operations with the exception that the memory slave address’
R/W bit is set to a one. There are three types of read operations;
current address, random and sequential.
Current Address Read (see Figure 13)
The PCA9501 contains an internal address counter that increments
after each read or write access, as a result if the last word accessed
was at address n then the address counter contains the address
n+1.
When the PCA9501 receives its memory slave address with the
R/W bit set to one it issues an acknowledge and uses the next eight
clocks to transmit the data contained at the address stored in the
address counter. The master ceases the transmission by issuing the
stop condition after the eighth bit. There is no ninth clock cycle for
the acknowledge.
Random Read (see Figure 14)
The PCA9501’s random read mode allows the address to be read
from to be specified by the master. This is done by performing a
dummy write to set the address counter to the location to be read.
2004 Sep 30
SDA
SDA
8-bit I
2-kbit EEPROM and 6 address pins
START CONDITION
START
CONDITION
S
S
SLAVE ADDRESS (MEMORY)
SLAVE ADDRESS (MEMORY)
1 A5 A4 A3 A2 A1 A0
1
2
C and SMBus I/O port with interrupt,
A5 A4 A3 A2 A1 A0
SDA
START CONDITION
R/W
R/W
S
1
0
1
SLAVE ADDRESS (MEMORY)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
A
A
A5
A4
DATA FROM MEMORY
WORD ADDRESS
A3
DATA n
A2
Figure 13. Current Address Read
A1 A0
ACKNOWLEDGE
Figure 15. Sequential Read
Figure 14. Random Read
FROM SLAVE
R/W
1
A
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
A
A
10
START
CONDITION
S
SLAVE ADDRESS (MEMORY)
The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the
acknowledge from the PCA9501 the master reissues the start
condition and memory slave address with the R/W bit set to one.
The PCA9501 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed
location. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.
Sequential Read (see Figure 15)
The PCA9501 sequential read is an extension of either the current
address read or random read. If the master doesn’t issue a stop
condition after it has received the eighth data bit, but instead issues
an acknowledge, the PCA9501 will increment the address counter
and use the next eight cycles to transmit the data from that location.
The master can continue this process to read the contents of the
entire memory. Upon reaching address 255 the counter will return to
address 0 and continue transmitting data until a stop condition is
received. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.
1 A5 A4 A3 A2 A1 A0
DATA FROM MEMORY
DATA FROM MEMORY
DATA n+1
R/W
ACKNOWLEDGE
FROM MASTER
1
A
SW00653
ACKNOWLEDGE
FROM SLAVE
A
STOP
CONDITION
P
DATA FROM MEMORY
DATA FROM MEMORY
DATA n+X
SW00655
PCA9501
Product data sheet
SW00654
STOP
CONDITION
STOP
CONDITION
P
P