MC803256K32L-6 MOSYS, MC803256K32L-6 Datasheet - Page 7

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MC803256K32L-6

Manufacturer Part Number
MC803256K32L-6
Description
Stand Alone Memories Based on Its 1T-SRAM Technology
Manufacturer
MOSYS
Datasheet
DS12, Rev 1.7 – 01/26/01
Data-Out
BW[4:1]
ADSC#
ADSP#
A[17:0]
Data-In
BWE#
ADV#
CE1#
GW#
OE#
CLK
CE2
tCES
tCES
tAS
© 2001 MoSys Inc., All Rights Reserved, 1020 Stewart Drive, Sunnyvale, CA 94086
tADSS
Single Write
WR1
tADSS
tAAS
tWS
tWS
tDS
tADSH
WR1
tCEH
tCEH
tAH
1a
ADV# Must be inactive for ADSP# write
tADSH
CE2 only sampled with ADSP# and ADSC#
WR2
tDH
tAAH
tWH
tWH
Figure 4 Write Cycle Timing
tKH
BW[4:1]# only are applied to first cycle of WR2
tKC
WR2
GW# allows processor addresses (and BE#=BW#)
to be pipelined during a writeback
tKL
2a
Preliminary Information
Burst Write
MC803256K32, MC803256K36
CE1# masks ADSP#
256Kx32/36 Pipeline Burst RAM
2b
ADSP# is blocked by CE1# inactive
2c
ADSC# initiated write
2d
Write
WR3
WR3
3a
Unselected
Unselected with CE2
Page 7

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