uda1338h-n1 NXP Semiconductors, uda1338h-n1 Datasheet - Page 38

• Manufacturer Part Number: uda1338h-n1
• Description: Multichannel Audio Coder-decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14389
Product data sheet
11.14 Supplemental settings 2
Table 59:
Table 60:
Table 61:
Table 62:
Bit
15 to 8
7
6 to 0
Bit
Symbol
Reset
default
Bit
Symbol
Reset
default
Bit
15 to 7
6 to 4
3 to 2
1
0
DITH2
0
0
0
0
1
1
1
1
Description of supplemental settings 1 register bits
Supplemental settings 2 register (address 31h)
Description of supplemental settings 2 register bits
DAC dither control bits
Symbol
-
DITH[2:0] DAC dither control. A 3-bit value to control the dithering of the SDAC.
-
VMTP
PDLNA
Symbol
-
PDT
-
15
-
0
7
-
0
Rev. 03 — 16 February 2005
14
-
0
6
DITH2
0
Description
default 0000 0000
Power-down time. A 1-bit value to select the time of the SDAC
power-down sequence. If bit PDT = 1, then 1024/f
(default), then 512/f
default 000 0000
Description
default 0000 0000 0
Default 000; see
default 00
Voice mute period control. A 1-bit value to select the voice ADC mute
period at power-up. If bit VMTP = 1, then mute for 1024 samples (1024/f
if bit VMTP = 0 (default), then mute for 2048 samples (2048/f
Power-down voice LNA. A 1-bit value to power-down the voice ADC
LNA. It should be noted that disabling the LNA requires a recovery time
defined by the external RC circuit. If bit PDNLA = 1, then power-down; if
bit PDNLA = 0 (default), then power-on.
DITH1
0
0
1
1
0
0
1
1
13
-
0
5
DITH1
0
Table
s
seconds.
12
-
0
4
DITH0
0
62.
DITH0
0
1
0
1
0
1
0
1
11
-
0
3
-
0
Multichannel audio coder-decoder
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
10
-
0
2
-
0
s
UDA1338H
Function
DC dither (MID-level);
default
reserved
reserved
reserved
DC dither (LOW-level)
DC plus AC dither
(LOW-level)
DC dither (HIGH-level)
DC plus AC dither
(HIGH-level)
seconds; if bit PDT = 0
9
-
0
1
VMTP
0
s
).
8
-
0
0
PDLNA
0
38 of 54
s
);