kad5610p Kenet Inc., kad5610p Datasheet - Page 21

• Manufacturer Part Number: kad5610p
• Description: Dual 10-bit, 250/210/170/125msps A/d Converter
• Manufacturer: Kenet Inc.

Address 0x02: burst_end
If a series of sequential registers are to be set, burst
mode can improve throughput by eliminating redun-
dant addressing. In 3-wire SPI mode the burst is
ended by pulling the CSB pin high. If the device is
operated in 2-wire mode the CSB pin is not available.
In that case, setting the burst_end address deter-
mines the end of the transfer. During a write opera-
tion, the user must be cautious to transmit the correct
number of bytes based on the starting and ending
addresses.
Bits 7:0 Burst End Address
DUT Information
Address 0x08: chip_id
Address 0x09: chip_version
The generic die identifier and a revision number, re-
spectively, can be read from these two registers.
Indexed DUT Configuration/Control
Address 0x10: device_index_A
A common SPI map, which can accommodate sin-
gle-channel or multi-channel devices, is used for all
Kenet ADC products. Certain configuration com-
mands (identified as Indexed in the SPI map) can be
executed on a per-converter basis. This register de-
termines which converter is being addressed for an
Indexed command. It is important to note that only a
single converter can be addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed.
Address 0x20: offset_coarse
Address 0x21: offset_fine
The input offset of each ADC core can be adjusted
in fine and coarse steps. Both adjustments are made
via an 8-bit word as detailed in Table 7. The data for-
mat is twos complement.
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incre-
mented or decremented value back to the same
register.
Rev 0.5.1 Preliminary
KAD5610P
This register value determines the ending ad-
dress of the burst data.
Address 0x22: gain_coarse
Address 0x23: gain_medium
Address 0x24: gain_fine
Gain of each ADC core can be adjusted in coarse,
medium and fine steps. Coarse gain is a 4-bit adjust-
ment while medium and fine are 8-bit. The data for-
mat is twos complement for all three registers.
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incre-
mented or decremented value back to the same
register.
Address 0x25: modes
Two distinct reduced power modes can be selected.
By default, the tri-level NAPSLP pin can select normal
Nominal Step Size
Mid–Scale (0x00)
+Full Scale (0x7F)
–Full Scale (0x80)
Table 9. Medium and Fine Gain Adjustments
Nominal Step Size
Mid–Scale (0x00)
+Full Scale (0x7F)
–Full Scale (0x80)
Parameter
Parameter
Steps
Steps
Table 8. Coarse Gain Adjustment
Nominal Step Size
–Full Scale (0x08)
Mid–Scale (0x00)
+Full Scale (0x07)
Table 7. Offset Adjustments
Parameter
Steps
Coarse Offset
Medium Gain
0x20[7:0]
+23.8mV
0x23[7:0]
-24.0mV
187.5µV
+10.48%
0.0825%
0.0mV
-10.56%
256
0.0%
256
Coarse Gain
0x22[3:0]
-11.2%
+9.8%
0.0%
1.4%
16
Fine Gain
0x24[7:0]
Fine Offset
0.00825%
0x21[7:0]
+1.05%
-1.06%
+1.7mV
-1.7mV
13.3µV
0.0%
0.0mV
256
256
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