tda8359j-n2 NXP Semiconductors, tda8359j-n2 Datasheet - Page 4

• Manufacturer Part Number: tda8359j-n2
• Description: Full Bridge Vertical Deflection Output Circuit In Lvdmos
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Vertical output stage
The vertical driver circuit has a bridge configuration. The
deflection coil is connected between the complimentary
driven output amplifiers. The differential input circuit is
voltage driven. The input circuit is specially designed for
direct connection to driver circuits delivering a differential
signal but it is also suitable for single-ended applications.
For processors with output currents, the currents are
converted to voltages by the conversion resistors
R
and INB. The differential input voltage is compared with
the voltage across the measuring resistor R
feedback information. The voltage across R
proportional with the output current. The relationship
between the differential input voltage and the output
current is defined by:
V
V
The output current should not exceed 3.2 A (p-p) and is
determined by the value of R
input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances. Depending on the values of R
internal bondwire resistance (typical value of 50 m ) the
actual value of the current in the deflection coil will be
approximately 5% lower than calculated.
Flyback supply
The flyback voltage is determined by the flyback supply
voltage V
allows to use an optimum supply voltage V
an optimum flyback supply voltage V
very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to V
to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short rise and
fall times of the flyback switch are determined mainly by
the slew rate value of more than 300 V/ s.
Protection
The output circuit contains protection circuits for:
2002 Jan 21
i(dif)(p-p)
i(dif)(p-p)
CV1
Full bridge vertical deflection output circuit
in LVDMOS
Too high die temperature
Overvoltage of output A.
and R
= I
= V
FB
CV2
o(p-p)
. The principle of two supply voltages (class G)
INA
(see Fig.5) connected to pins INA
V
R
INB
M
M
and R
FB
CV
. The allowable
for flyback, thus
M
P
M
M
for scan and
and the
, providing
is
FB
, due
4
Guard circuit
A guard circuit with output pin GUARD is provided.
The guard circuit generates a HIGH-level during the
flyback period. The guard circuit is also activated for one
of the following conditions:
The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.
Damping resistor compensation
HF loop stability is achieved by connecting a damping
resistor R
in R
Both the resistor current and the deflection coil current flow
into measuring resistor R
coil current at the start of the scan.
The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time. For
that purpose a compensation resistor R
a zener diode is connected between pins OUTA and INA
(see Fig.4). The zener diode voltage value should be
equal to V
where:
R
CMP
During thermal protection (T
During an open-loop condition.
V
at flyback
R
V
loss(FB)
Z
coil
D1
is the voltage of zener diode D4.
during scan and flyback are significantly different.
is the deflection coil resistance
=
D1
----------------------------------------------------------------------------------------------------------- -
P
V
is the voltage loss between pins V
. The value of R
FB
across the deflection coil. The current values
V
FB
–
V
–
loss FB
V
loss FB
M
–
, resulting in a too low deflection
CMP
I
coil peak
–
V
j
is calculated by:
Z
170 C)
R
Product specification
D1
TDA8359J
R
CMP
coil
R
in series with
FB
CV1
and OUTA
R
M