tda8034at NXP Semiconductors, tda8034at Datasheet - Page 8

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tda8034at

Manufacturer Part Number
tda8034at
Description
Smart Card Interface
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
TDA8034T_TDA8034AT_1
Product data sheet
8.5 Shutdown mode
8.6 Activation sequence
After a power-on reset, if pin CMDVCCN is HIGH, the circuit enters the Shutdown mode,
ensuring only the minimum number of circuits are active while the TDA8034T/TDA8034AT
waits for the microcontroller to start a session.
The following device activation sequence is applied when using an external clock; see
Figure
Calculation of the time delays is as follows:
Remark: The value of period T is 64 times the period interval of the internal oscillator at
high frequency (
1. Pin CMDVCCN is pulled LOW (t0).
2. The internal oscillator is triggered (t0).
3. The internal oscillator changes to high frequency (t1).
4. V
5. Pin I/O is driven HIGH (t3).
6. The clock on pin CLK is applied to the C3 contact (t4).
7. Pin RST is enabled (t5).
all card contacts are inactive. The impedance between the contacts and GND is
approximately 200 .
pin I/OUC is high-impedance using the 11 k pull-up resistor connected to V
the voltage generators are stopped
the voltage supervisor is active
the internal oscillator runs at its lowest frequency (f
t1 = t0 + 384
t2 = t1
t3 = t1 + 17T / 2
t4 = driven by host controller; > t3 and < t5
t5 = t1 + 23T / 2
CC
6:
rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2).
1
fosc(int)high
1
fosc(int)low
Rev. 01 — 5 February 2010
); t3 is called t
TDA8034T; TDA8034AT
d(start)
and t5 is called t
osc(int)low
)
d(end)
Smart card interface
.
© NXP B.V. 2010. All rights reserved.
DD(INTF)
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