tda8025hn NXP Semiconductors, tda8025hn Datasheet
tda8025hn
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tda8025hn Summary of contents
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TDA8025 IC card interface Rev. 01 — 6 April 2009 1. General description The TDA8025 is a cost-effective analog interface for asynchronous smart cards operating 1 optionally, 1.2 V. Using few external components, the TDA8025 ...
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... NXP Semiconductors 4. Quick reference data Table 1. Quick reference data Symbol Parameter Supplies V regulator input DDI(REG) supply voltage V interface supply DD(INTF) voltage I regulator input DDI(REG) supply current Card supply voltage V supply voltage CC V peak-to-peak ripple ripple(p-p) voltage TDA8025_1 Product data sheet ...
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... Section 8.1 on page 7 DD(INTREGD) the limits of XTAL1. [2] See Figure 12 on page 18. 5. Ordering information Table 2. Ordering information Type number Package Name TDA8025HN HVQFN32 TDA8025_1 Product data sheet …continued Conditions 1 1 down total sequence +85 C amb for specifi ...
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... NXP Semiconductors 6. Block diagram V DD(INTF) R1 PORADJ 25 ( PRES 9 PRESN 22 RSTIN 1 CMDVCCN 23 OFFN 6 CLKDIV1 INTERFACE 5 CLKDIV2 26 ENCLKIN 7 VCC_SEL1 8 VCC_SEL2 4 100 nF V DD(INTF) (1) Optional external resistor bridge. If this bridge is not needed, connect pin PORADJ to V Fig 1. Block diagram TDA8025_1 Product data sheet ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. 7.2 Pin description Table 3. Symbol CMDVCCN TEST1 TEST2 V DD(INTF) CLKDIV2 CLKDIV1 VCC_SEL1 VCC_SEL2 PRESN PRES I/O AUX2 AUX1 TDA8025_1 Product data sheet terminal 1 index area CMDVCCN 1 TEST1 2 3 TEST2 V 4 DD(INTF) TDA8025 CLKDIV2 5 6 CLKDIV1 7 VCC_SEL1 VCC_SEL2 ...
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... NXP Semiconductors Table 3. Symbol CGND CLK CONFIG RST DD(INTREGD) GND V DDI(REG) RSTIN OFFN TEST3 PORADJ ENCLKIN XTAL2 XTAL1 I/OUC AUX1UC AUX2UC TEST4 [ input output, I/O = input/output ground and P = power supply. [2] If pin PRESN or pin PRES is true, the card is considered to be present. During card insertion, debouncing can occur on these signals ...
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... NXP Semiconductors 8. Functional description Remark: Throughout this document the ISO7816 terminology conventions have been adhered to and it is assumed that the reader is familiar with these. 8.1 Power supplies Two supply selections can be made using pin CONFIG (see active state of the pin: • pin CONFIG is LOW: supply is pin V 3.6 V and 5.5 V. The regulator output range is between 3 V and 3.6 V. • ...
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... NXP Semiconductors After powering up the device, pin OFFN remains LOW until pins CMDVCCN and PRES are both HIGH or pin CMDVCCN is HIGH and pin PRESN is LOW. During power off, pin OFFN is driven LOW when V When pin CMDVCCN is HIGH, the internal oscillator frequency (f frequency (inactive) mode to reduce power consumption ...
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... NXP Semiconductors 8.2.3 V DD(INTREGD) The TDA8025 remains in inactive mode irrespective of the levels on the command lines when • V DD(INTREGD) • Pin PORADJ (monitoring V In both cases, this lasts for the duration of t and V DD(INTF) voltages (V • V DD(INTREGD) for the digital part of the TDA8025 • ...
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... NXP Semiconductors The voltage on PORADJ (V where: • V DD(INTF) • ratio = --------------- - 1 An activation can be triggered INTF where • V th(max) The resistance spread of R1 between a minimum value R1 R1 induces a spread of the ratio . This is also true for R2. Based on this: max V DD INTF actmin ...
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... NXP Semiconductors R1 nom -------------- - R2 nom R2 nom If we target 1 % accuracy resistors ( = 0.01) and R Table 8 on page • R1 nom • R2 nom Deactivation always occurs when V PORADJ where • V th(min) • V DD(INTF)deactmax occurs • max = max With the resulting values for R1 page 23) then V 8.3 Clock circuits The clock signal (pin CLK) to the card is either generated by the clock signal input on pin XTAL1 or from a crystal (f voltage level applied to pin ENCLKIN defi ...
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... NXP Semiconductors The duty cycle on pin CLK should be between 45 % and ensure this, the following must be applied: • when the CLK frequency external clock is connected to pin XTAL1, the duty cycle should be between 48 % and 52 % with an input signal period transition time of less than 5 %. ...
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... NXP Semiconductors 8.4 Input and output circuits When pins I/O and I/OUC are driven HIGH using resistor between pins I/O and V and/or between pins I/OUC and V CC referenced to V The first side on which a falling edge occurs becomes the master. An anti-latch circuit disables falling edge detection on the other line, making it the slave. After a time delay t , the NMOS transistor on the slave-side is turned on ...
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... NXP Semiconductors 8.6 Activation sequence After the power-on and internal pulse width delay, the microcontroller checks the presence of the card using signal OFFN. • The card is present when pins OFFN and CMDVCCN are HIGH • The card is not present when pin OFFN is LOW and pin CMDVCCN is HIGH If the card is in the reader (either pin PRESN or pin PRES is true), the microcontroller can start a card session by pulling pin CMDVCCN LOW ...
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... NXP Semiconductors CMDVCCN XTAL V CC I/O CLK RSTIN RST I/OUC OSCINT Fig 8. CMDVCCN XTAL V CC I/O CLK RSTIN RST I/OUC OSCINT Fig 9. The following sequence occurs when using an external clock connected to pin XTAL1 (see Figure 10): 1. external clock (XTAL1) started by the microcontroller (t0) 2 ...
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... NXP Semiconductors 4. pins I/O, AUX1 and AUX2 are enabled (t3) 5. CLK is applied to the C3 contact (t4) 6. pin RST is enabled (t5) Calculation of the time delays is as follows: • 2.13 ms • 3T • 5T/2 • driven by the host controller; > t3 and < t5 • 11T/2 Remark: The value of period times the period interval of the internal oscillator (i.e. ...
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... NXP Semiconductors CMDVCCN XTAL1 V CC I/O CLK RSTIN RST I/OUC OSCINT Fig 11. Activation sequence: CLK not controlled by pin RSTIN and with an external clock 8.7 Active mode When the activation sequence has finished, the TDA8025 is in active mode. This mode enables data exchange between the card and the microcontroller using the input and output lines ...
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... NXP Semiconductors 8.8 Deactivation sequence When a session is completed, the microcontroller sets pin CMDVCCN to HIGH. The circuit then executes an automatic deactivation sequence by counting the sequencer back to the inactive state (see 1. pin RST is pulled LOW (t11) 2. the clock is stopped, pin CLK is LOW (t12) 3. pins I/O, AUX1 and AUX2 are pulled LOW (t13) 4 ...
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... NXP Semiconductors CMDVCCN RST CLK I XTAL1 OSCINT Fig 13. Deactivation sequence with an external clock connected to pin XTAL1 8.9 V regulator CC Table 5. VCC_SEL1 The V CC • • 1.8 V • 1.2 V The V CC This detection is filtered, enabling spurious current pulses up to 200 mA with a duration 200 drawn by the card without causing deactivation ...
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... NXP Semiconductors • V DD(INTF) • Overheating Fault detection monitors two different situations (see 1. Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in the reader and HIGH if the card is in the reader. Any supply voltage drop on V DD(INTREGD) internal power-on reset pulse but does not act upon the pin OFFN signal. The card is not powered-up and as such short-circuits and overheating are not detected ...
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... NXP Semiconductors PRES OFFN CMDVCCN V CC (1) Deactivation caused by card removal. (2) Deactivation caused by short circuit. Fig 15. Operation of debounce feature pin OFFN in combination with pins CMDVCCN, TDA8025_1 Product data sheet t deb PRES and V CC Rev. 01 — 6 April 2009 TDA8025 IC card interface t deb (1) © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 9. Limiting values Remark: All card contacts are protected against any short-circuit to any other card contact. Stress beyond the levels indicated in the device. This is a short-term stress rating only and under no circumstances implies functional operation under long-term stress conditions. Table 6. ...
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... NXP Semiconductors 11. Characteristics Table 8. Characteristics of IC supply voltage all parameters remain within limits but are only statistically tested for the temperature range; f amb currents flowing into the IC are positive; unless otherwise specified. Parameters specifi function DD(INTF) ...
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... NXP Semiconductors Table 8. Characteristics of IC supply voltage all parameters remain within limits but are only statistically tested for the temperature range; f amb currents flowing into the IC are positive; unless otherwise specified. Parameters specifi function DD(INTF) ...
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... NXP Semiconductors Table 8. Characteristics of IC supply voltage all parameters remain within limits but are only statistically tested for the temperature range; f amb currents flowing into the IC are positive; unless otherwise specified. Parameters specifi function DD(INTF) ...
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... NXP Semiconductors Table 8. Characteristics of IC supply voltage all parameters remain within limits but are only statistically tested for the temperature range; f amb currents flowing into the IC are positive; unless otherwise specified. Parameters specifi function DD(INTF) ...
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... NXP Semiconductors Table 8. Characteristics of IC supply voltage all parameters remain within limits but are only statistically tested for the temperature range; f amb currents flowing into the IC are positive; unless otherwise specified. Parameters specifi function DD(INTF) ...
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... NXP Semiconductors Table 8. Characteristics of IC supply voltage all parameters remain within limits but are only statistically tested for the temperature range; f amb currents flowing into the IC are positive; unless otherwise specified. Parameters specifi function DD(INTF) ...
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... NXP Semiconductors [2] To enable the microcontroller to provide the required maximum voltage input level on XTAL1 0.3 V. See Section 8.1 on page 7 DD(INTREGD) the limits of XTAL1. [3] To meet these specifications and one of 220 nF with an ESR of < 100 m . [4] Using the internal pull-up resistor to V ...
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... NXP Semiconductors Fig 16. Definition of output and input transition times TDA8025_1 Product data sheet Rev. 01 — 6 April 2009 TDA8025 IC card interface )/ 001aai973 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 12. Application information V DD(INTF) Fig 17. Application diagram (3 V < V TDA8025_1 Product data sheet MICROCONTROLLER V DD(INTF) CMDVCCN 1 TEST1 2 TEST2 C5 3 100 nF V DD(INTF) 4 CLKDIV2 5 CLKDIV1 6 VCC_SEL1 7 VCC_SEL2 8 Refer to Table 8 on page 23 and Section 8.1 “Power supplies” on page 7 the V restrictions. DD(INTF) DDI(REG) Rev. 01 — ...
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... NXP Semiconductors V DD(INTF) Fig 18. Application diagram (3.6 V < V TDA8025_1 Product data sheet MICROCONTROLLER V DD(INTF) CMDVCCN 1 TEST1 2 TEST2 C5 3 100 nF V DD(INTF) 4 CLKDIV2 5 CLKDIV1 6 VCC_SEL1 7 VCC_SEL2 8 Refer to Table 8 on page 23 and Section 8.1 “Power supplies” on page 7 the V restrictions. DD(INTF) DDI(REG) Rev. 01 — 6 April 2009 ...
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... NXP Semiconductors 13. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 20. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 13. Acronym ATR ESD ESR NMOS POR PMOS 16. Revision history Table 14. Revision history ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 7 8.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2 Voltage supervisors . . . . . . . . . . . . . . . . . . . . . 8 8.2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2.3 V voltage supervisor with DD(INTREGD) pin PORADJ connected ...