tda8594sd-n1 NXP Semiconductors, tda8594sd-n1 Datasheet - Page 16
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tda8594sd-n1
Manufacturer Part Number
tda8594sd-n1
Description
Tda8594 I?c-bus Controlled 4 X 50 W Power Amplifier
Manufacturer
NXP Semiconductors
Datasheet
1.TDA8594SD-N1.pdf
(48 pages)
NXP Semiconductors
TDA8594_2
Product data sheet
7.14 Offset detection
7.15 DC load detection
Table 4.
The offset detection can be performed with no input signal (for instance when the digital
signal processor is in mute after a start-up) or with an input signal. In I
I
When the amplifier BTL output voltage is within a window with a threshold of 1.75 V
typical, the latches DBx[D2] are reset and setting is disabled. If, for instance, after 1
second an I
not crossed the offset threshold during the last 1 second (see
the applied frequency is below 1 Hz (I
more than 1.75 V is present.
When the DC load detection is enabled with IB1[D1], a DC offset is slowly applied at the
output of the amplifiers during the start-up cycle and the load currents are measured.
Different load levels will be detected to differentiate between normal load, line driver load
or open load.
Diagnostic information I
Offset detection
Load detection
Overvoltage
2
Fig 11. Offset detection
C-bus read of the output offset is performed, the I
Diagnostic information availability
2
C-bus read is performed again and the offset bits are still set, the output has
Rev. 02 — 11 December 2007
offset
threshold
offset
threshold
I
2
C-bus mode only
DIAG pin
no
no
yes
2
C-bus mode
read = set bit
2
C-bus read interval = 1 s) or an output offset of
disabled
V
V
setting
reset:
O
O
= V
= V
I
2
OUT+
OUT+
…continued
C-bus controlled 4
V
V
OUT
OUT
DB1 bit D2 set
2
read = offset
C-bus latches DBx[D2] will be set.
STB pin
no
no
no
t = 1 s:
t = 1 s:
read = no offset
DB1 bit D2 reset
t
t
001aad175
Figure
50 W power amplifier
Legacy mode
DIAG pin
no
no
yes
11). This can mean
2
TDA8594
C-bus mode, if an
© NXP B.V. 2007. All rights reserved.
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