tda8752ah/6 NXP Semiconductors, tda8752ah/6 Datasheet - Page 24

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tda8752ah/6

Manufacturer Part Number
tda8752ah/6
Description
Triple High-speed Analog-to-digital Converter Adc
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
1999 Feb 24
G
I
t
V
t
t
G
Clamps
P
t
t
t
CLP
A
Phase-locked loop
j
DR
f
f
GC
stab
r(Vi)
f(Vi)
COR1
COR2
W(CLP)
PLL(rms)
ref
PLL
SYMBOL
G
i(p-p)
CLP
off
Triple high-speed Analog-to-Digital
Converter (ADC)
FINE
E(rms)
amp
E
/T
fine gain correction range
amplifier gain stability as a
function of temperature
gain current
amplifier gain adjustment
speed
input voltage range
(peak-to-peak value)
input voltage rise time
input voltage fall time
channel-to-channel gain
matching (RMS value)
precision
clamp correction time to within
clamp correction time to less
than 1 LSB
clamp pulse width
channel-to-channel clamp
matching
code clamp reference
long term PLL jitter
(RMS value)
divider ratio
reference clock frequency
range
output clock frequency range
10 mV
PARAMETER
fine register input code = 0;
(see Fig.9)
fine register input
code = 31; (see Fig.9)
V
100 ppm/ C maximum
variation
HSYNC active; capacitors
on pins 8, 16 and 24 = 22 nF
corresponding to full-scale
output
f
f
maximum coarse gain;
T
minimum coarse gain;
T
black level noise on RGB
channels = 10 mV (max.)
(RMS value); T
variation; clamp
capacitor = 4.7 nF
variation; clamp
capacitor = 4.7 nF
clamp register input
code = 0
clamp register input
code = 255
f
f
see Table 13
i
i
CLK
CLK
100 mV black level input
100 mV black level input
amb
amb
ref
= 100 MHz; square wave
= 100 MHz; square wave
= 2.5 V with
= 60 MHz; see Table 13
= 100 MHz;
= 25 C
= 25 C
CONDITIONS
24
amb
= 25 C
0.4
500
100
15
12
MIN.
1
1
0
25
1
2
64
450
360
0.5
20
63.5
TYP.
Product specification
200
1.2
2.5
2.5
+1
300
10
2000
+1
4095
280
100
TDA8752A
MAX.
dB
dB
ppm/ C
mdB/ s
V
ns
ns
%
%
LSB
ns
lines
ns
LSB
LSB
LSB
ps
ps
kHz
MHz
A
UNIT

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