tda8752b-03 NXP Semiconductors, tda8752b-03 Datasheet - Page 19

• Manufacturer Part Number: tda8752b-03
• Description: Tda8752b Triple High-speed Analog-to-digital Converter 110 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 07338
Product specification
9.1.3 Control register
9.1.4 VCO register
Table 7:
The default programmed value is: N
COAST and HSYNC signals can be inverted by setting the I
‘Vlevel’ and ‘Hlevel’ respectively. When ‘Vlevel’ and ‘Hlevel’ are set to zero
respectively, COAST and HSYNC are active HIGH.
The bit ‘Edge’ defines the rising or falling edge of CKREF to synchronize the PLL. It
will be on the rising edge if the bit is at logic 0 and on the falling edge if the bit is at
logic 1.
The bits ‘Up’ and ‘Do’ are used for the test, to force the charge pump current. These
bits have to be logic 0 during normal use.
The bits ‘Ip0’, ‘Ip1’ and ‘Ip2’ control the charge pump current, to increase the
bandwidth of the PLL, as shown in
Table 8:
The default programmed value is as follows:
The bits ‘Z2’, ‘Z1’ and ‘Z0’ enable the internal resistance for the VCO filter to be
selected.
N
0
31
Ip2
0
0
0
0
1
1
1
1
•
•
•
•
FINE
Charge pump current = 100 A
Test bits: no test mode; bits ‘Up’ and ‘Do’ at logic 0
Rising edge of CKREF: bit ‘Edge’ at logic 0
COAST and HSYNC inputs are active HIGH: bits ‘Vlevel’ and ‘Hlevel’ at logic 0.
Gain correspondence (FINE)
Charge pump current control
Rev. 03 — 21 July 2000
Ip1
0
0
1
1
0
0
1
1
Triple high-speed Analog-to-Digital Converter 110 Msps
Gain
0.825
0.878
Table
FINE
= 0.
8.
Ip0
0
1
0
1
0
1
0
1
V
1.212
1.139
i
to be full-scale (V)
© Philips Electronics N.V. 2000. All rights reserved.
2
C-bus control bits
TDA8752B
Current ( A)
6.25
12.5
25
50
100
200
400
700
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