tda8752b-03 NXP Semiconductors, tda8752b-03 Datasheet - Page 12

• Manufacturer Part Number: tda8752b-03
• Description: Tda8752b Triple High-speed Analog-to-digital Converter 110 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 07338
Product specification
Fig 6. Coarse gain control.
The calibration of the gains is done using the following principle.
From the reference voltage V
generated internally. During the synchronization part of the video line, the multiplexer,
controlled by the TTL synchronization signal (HSYNCI, coming from HSYNC;
see
signal coming from a synchronization separator), is switched between the two
amplifiers.
The output of the multiplexer is either the normal video signal or the 0.156 V
reference signal (during HSYNC).
The corresponding ADC outputs are then compared to a preset value loaded in a
register. Depending on the result of the comparison, the gain of the variable gain
amplifiers is adjusted (coarse gain control; see
registers receive data via a serial interface to enable the gain to be programmed.
The preset value loaded in the 7-bit register is chosen between approximately
67 codes to ensure the full-scale input range (see
achieved using these registers. In this case care should be taken to stay within the
allowed code range (32 to 99).
A fine correction using three 5-bit DACs, also controlled via the serial interface, is
used to fine tune the gain of the three channels (fine gain control; see
and to compensate the channel-to-channel gain mismatch.
With a full-scale ADC input, the resolution of the fine register corresponds to
peak-to-peak variation.
To use these gain controls correctly, it is recommended to fix the coarse gain (to have
a full-scale ADC input signal) to within 4 LSB and then adjust it with the fine gain. The
gain is adjusted during HSYNC. During this time the output signal is not related to the
amplified input signal. The outputs, when the coarse gain system is stable, are
related to the programmed coarse code (see
(67 codes)
register
Figure
coarse
v
alue
N COARSE
code
1) with a width equal to one of the video synchronization signals (e.g. the
127
99
32
0
0.156 =
Rev. 03 — 21 July 2000
G (max)
V ref
16
Triple high-speed Analog-to-Digital Converter 110 Msps
0.2
ref
a reference signal of 0.156 V (p-p) (
G (min)
0.6
Figure
255
227
160
128
ADC output
Figure 2
code
Figure
V i (p-p)
FCE472
2
6).
and 6). The three 7-bit
6). A contrast control can be
© Philips Electronics N.V. 2000. All rights reserved.
TDA8752B
1
16
Figure 2
V
ref
) is
1
and 7)
2
12 of 38
LSB