adc1443d NXP Semiconductors, adc1443d Datasheet - Page 30

• Manufacturer Part Number: adc1443d
• Description: Dual Channel 14-bit Adc; 125, 160 Or 200 Msps; Jesd204b-compliant Cgvxpress Serial Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 16.
[1]
ADC1443D_SER
Objective data sheet
CFG_SETUP[3:0] ADC A ADC B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
JESD204A/JESD204B configuration table
11.4 Configuration pins (CFG0, CFG1, CFG2, CFG3)
OFF
OFF
OFF
ON
ON
ON
ON
ON
The configuration pins are only active as inputs at start-up. The values on those pins are
read once to set up the device. Then the pins become outputs (OTRA and OTRB) and any
change in the configuration is applied by SPI.
OFF
OFF
OFF
ON
ON
ON
ON
ON
Lane 0
OFF
OFF
OFF
OFF
ON
ON
ON
ON
All information provided in this document is subject to legal disclaimers.
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Rev. 1 — 28 September 2011
Lane 1
OFF
OFF
OFF
OFF
ON
ON
ON
ON
F
2
4
4
2
2
2
2
2
[1]
HD
0
0
0
0
0
0
0
0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
[1]
K
9
5
5
9
9
9
9
9
[1]
M
2
2
2
1
1
1
1
2
[1]
ADC1443D series
L
2
1
1
1
1
1
1
2
[1]
power-down
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
Comment
chip
© NXP B.V. 2011. All rights reserved.
CS
1
1
1
1
1
1
1
1
[1]
CF
0
0
0
0
0
0
0
0
[1]
30 of 50
S
1
1
1
1
1
1
1
1
[1]