adc1206s040 NXP Semiconductors, adc1206s040 Datasheet - Page 12

• Manufacturer Part Number: adc1206s040
• Description: Single 12 Bits Adc, Up To 40 Mhz, 55 Mhz Or 70 Mhz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 6.
V
V
V
and V
[1]
[2]
[3]
[4]
[5]
[6]
ADC1206S040_055_070_2
Product data sheet
Symbol
Bit error rate (f
BER
Timing (C
t
t
t
3-state output delay times; see
t
t
t
t
d(s)
h(o)
d(o)
dZH
dZL
dHZ
dLZ
CCA
CCO
I(IN)(p-p)
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC level vary 1:1 with V
b) PECL mode 2: (DC level vary 1:1 with V
c) PECL mode 3: (DC level vary 1:1 with V
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p - p) and with a DC
e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
The ADC input range can be adjusted with an external reference connected to V
see
The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics:
THD
where
Signal-to-noise ratio (S/N) takes into account all harmonics above five and noise up to Nyquist frequency; see
= V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; V
= V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; T
CCO
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal,
sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a
100 nF capacitor.
In that case the CLKN pin has to be connected to the ground.
Figure
=
= 3.3 V, T
V
L
1H
Characteristics
20 log
I(INN)(p-p)
= 10 pF)
Parameter
bit error rate
sampling delay
time
output hold
time
output delay
time
float to active
HIGH delay
time
float to active
LOW delay
time
active HIGH to
float delay time
active LOW to
float delay time
is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see
12.
clk
= 55 MHz)
----------------------------------------------------------------------------------------------------------------------------------------------- -
amb
= 1.9 V; V
[9]
2H
= 25 C and C
2
+
…continued
Conditions
f
code 2047
ref
i
= 20 MHz; V
3H
= V
Figure 4
2
CCA3
+
L
= 10 pF; unless otherwise specified.
4H
1H
CCD
CCD
CCD
1.75 V; V
I
= 16 LSB at
) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
) CLK and CLKN inputs are at differential PECL levels.
) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
2
2
+
Rev. 02 — 12 August 2008
5H
I(cm)
2
= V
+
CCA3
Test
[1]
C
C
C
C
C
C
C
C
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
6H
CCD
2
Min
-
-
4
-
-
-
-
-
1.6 V; typical values measured at V
= V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
ADC1206S040/055/070
amb
ref
pin. This voltage has to be referenced to V
= 40 C to 85 C;
Typ
10
0.25
6.4
9.0
5.1
7.0
9.7
9.5
14
Figure
6.
Max
-
1
-
13
9.0
11
14
13
Figure
CCA
© NXP B.V. 2008. All rights reserved.
= V
8.
Unit
times/sample
ns
ns
ns
ns
ns
ns
ns
CCD
= 5 V
CCA
12 of 32
;