adc1213s125hn/c1 NXP Semiconductors, adc1213s125hn/c1 Datasheet - Page 21

• Manufacturer Part Number: adc1213s125hn/c1
• Description: Adc1213s Series Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Serial Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1213S_SER
Product data sheet
Fig 21. General overview of the JESD204A serializer
S samples per frame cycle
SYNC~
CS bits for control
N bits from Cr
M CONVERTERS
N' = N + CS
0
11.5.1 Digital JESD204A formatter
+
11.5 JESD204A serializer
M
×
(N'
×
For more information about the JESD204A standard refer to the JEDEC web site.
The block placed after the ADC core is used to implement all functions of the JESD204A
standard. This ensures signal integrity and guarantees the clock and the data recovery at
the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
S) bits
TX transport layer
Fig 20. CML output connection to the receiver (AC-coupling)
CF: position of controls bits
Padding with Tails bits (TT)
HD: frame boundary break
L LANES
All information provided in this document is subject to legal disclaimers.
F octets
+
L
50 Ω
×
(F) octets
Rev. 1 — 14 March 2011
OCTETS
FRAME
V
DDD
TO
12 mA to 26 mA
L octets
50 Ω
SCRAMBLER
-
CMLN
CMLP
Single 12-bit ADC; serial JESD204A interface
10 nF
10 nF
TX CONTROLLER
CHARACTER
GENERATOR
ALIGNMENT
ADC1213S series
100 Ω
10-bit
8-bit/
RECEIVER
005aaa187
© NXP B.V. 2011. All rights reserved.
005aaa198
SER
LANE 0
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