adc1213s125hn/c1 NXP Semiconductors, adc1213s125hn/c1 Datasheet
adc1213s125hn/c1
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adc1213s125hn/c1 Summary of contents
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ADC1213S series Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface Rev. 1 — 14 March 2011 1. General description The ADC1213S is a single channel 12-bit Analog-to-Digital Converter (ADC) optimized for high dynamic ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Sampling frequency (Msps) ADC1213S125HN/C1 125 ADC1213S105HN/C1 105 ADC1213S080HN/C1 80 ADC1213S065HN/C1 65 ADC1213S_SER Product data sheet Single 12-bit ADC; serial JESD204A interface Package Name Description HVQFN32R plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; resin based; ...
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... NXP Semiconductors 5. Block diagram CLKP DLL PLL CLKM CORRECTION AND INP T/H INPUT STAGE INM STAGE AND DUTY ADC1213S Fig 1. Block diagram ADC1213S_SER Product data sheet SCLK ERROR DIGITAL PROCESSING OTR ADC CORE 12-BIT D11 to D0 PIPELINED CLOCK INPUT CYCLE CONTROL OTR All information provided in this document is subject to legal disclaimers. Rev. 1 — ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Symbol CLKP CLKM AGND REFB REFT VCM INM INP VDDA VDDA SCLK SDIO ADC1213S_SER Product data sheet terminal 1 index area CLKP 1 CLKM 2 AGND 3 REFB 4 REFT 5 VCM 6 INM 7 INP 8 Transparent top view Pinning diagram ...
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... NXP Semiconductors Table 2. Symbol CS OTR VDDD DGND DGND VDDD CMLP CMLN VDDD DGND DGND n.c. SYNCP SYNCN VDDD DGND VDDA AGND SENSE VREF [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 3. In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics Symbol Parameter Supplies V analog supply voltage DDA V digital supply voltage DDD(1V8) (1 analog supply current DDA I digital supply current DDD(1V8) (1 total power dissipation tot P power dissipation Clock inputs: pins CLKP and CLKM (AC-coupled) ...
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... NXP Semiconductors Table 5. Static characteristics Symbol Parameter Voltage controlled regulator output: pin VCM V common-mode output O(cm) voltage I common-mode output O(cm) current Reference voltage input/output: pin VREF V voltage on pin VREF VREF Data outputs: pins CMLP, CMLN Output levels 1.8 V; SWING_SEL[2:0] = 000 DDD(1V8) V LOW-level output ...
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... NXP Semiconductors Table 5. Static characteristics Symbol Parameter E gain error G Supply PSRR power supply rejection ratio [1] Typical values measured at V DDA = −40 °C to +85 ° range T amb applied to serial outputs; unless otherwise specified. ADC1213S_SER Product data sheet [1] …continued Conditions full-scale 200 mV (p-p) on pin VDDA ...
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Dynamic characteristics 10.1 Dynamic characteristics [1] Table 6. Dynamic characteristics Symbol Parameter Conditions α second harmonic MHz 2H i level MHz MHz 170 MHz i α ...
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Table 6. Dynamic characteristics …continued Symbol Parameter Conditions IMD intermodulation MHz i distortion MHz MHz 170 MHz i α channel crosstalk MHz ct(ch) ...
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... NXP Semiconductors 10.3 Serial output timing The eye diagram of the serial output is shown in are: • 3.125 Gbps data rate • T amb • DC-coupling with two different receiver common-mode voltages Fig 3. Fig 4. ADC1213S_SER Product data sheet = 25 °C Eye diagram receiver common-mode Eye diagram receiver common-mode All information provided in this document is subject to legal disclaimers. Rev. 1 — ...
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... NXP Semiconductors 10.4 SPI timing Table 8. Symbol t w(SCLK) t w(SCLKH) t w(SCLKL clk(max) [1] Typical values measured at V are across the full temperature range T V i(INP) otherwise specified. Fig 5. ADC1213S_SER Product data sheet [1] SPI timing characteristics Parameter Conditions SCLK pulse width SCLK HIGH pulse ...
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... NXP Semiconductors 11. Application information 11.1 Analog inputs 11.1.1 Input stage description The analog input of the ADC1213S supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (V The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) ...
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... NXP Semiconductors Fig 7. The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 9. Input frequency (MHz) 11.1.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Fig 8. ADC1213S_SER Product data sheet ...
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... NXP Semiconductors The configuration shown in both cases, the choice of transformer is a compromise between cost and performance. Fig 9. 11.2 System reference and power management 11.2.1 Internal/external reference The ADC1213S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (see control bits INTREF[2:0] (when bit INTREF_EN = logic 1 ...
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... NXP Semiconductors VREF SENSE Fig 10. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 10. Mode Internal Internal Internal, SPI mode (Figure External Figure 11 required reference voltage source. ADC1213S_SER Product data sheet REFERENCE AMP EXT_ref ...
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... NXP Semiconductors VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE Fig 11. Internal reference (p-p) full-scale VREF 330 pF REFERENCE EQUIVALENT SENSE Fig 13. Internal reference via SPI (p- (p-p) full-scale 11.2.2 Programmable full-scale The full-scale is programmable between 1 V (p- (p-p) (see Table 11. INTREF[2:0] 000 001 010 011 ...
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... NXP Semiconductors Fig 15. Reference equivalent schematic 11.2.4 Biasing The common-mode input voltage (V 0.5V DDA 11.3 Clock input 11.3.1 Drive modes The ADC1213S can be driven differentially (LVPECL). It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor). a. Rising edge LVCMOS Fig 16 ...
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... NXP Semiconductors a. Sine clock input c. LVPECL clock input Fig 17. Differential clock input 11.3.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in voltage of the differential input stage is set via internal 5 kΩ resistors. Fig 18. Equivalent input circuit ADC1213S_SER Product data sheet ...
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... NXP Semiconductors Single-ended or differential clock inputs can be selected via the SPI (see single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin should be connected to ground via a capacitor. 11.3.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performance of the ADC by compensating the input clock signal duty cycle ...
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... NXP Semiconductors Fig 20. CML output connection to the receiver (AC-coupling) 11.5 JESD204A serializer For more information about the JESD204A standard refer to the JEDEC web site. 11.5.1 Digital JESD204A formatter The block placed after the ADC core is used to implement all functions of the JESD204A standard. This ensures signal integrity and guarantees the clock and the data recovery at the receiver side ...
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... NXP Semiconductors ADC_MODE[1:0] PRBS 11 N DUMMY AND CS ADC_PD ADC ASSEMBLY × 1 frame CLK PLL AND × F character CLK DLL × 10F bit CLK Fig 22. Detailed view of the JESD204A serializer with debug functionality 11.5.2 ADC core output codes versus input voltage Table 13 Table 13 ...
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... NXP Semiconductors 11.6 Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1213S serial interface is a synchronous serial communications port allowing for easy interfacing with many industry microprocessors. It provides access to the registers that control the operation of the chip in both read and write modes. This interface is configured as a 3-wire type (SDIO as bidirectional pin). ...
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... NXP Semiconductors CS SCLK SDIO R A12 A11 A10 A9 Fig 23. Transfer diagram for two data bytes (3-wire type) ADC1213S_SER Product data sheet Instruction bytes All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 ADC1213S series Single 12-bit ADC ...
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Channel control Table 17. Register allocation map [1] Address Register name Access (hex) Bit 7 ADC control register 0003 SPI control R/W - 0005 Reset and R/W SW_RST Operating modes 0006 Clock R/W - 0008 Vref R/W - 0013 ...
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Table 17. Register allocation map …continued [1] Address Register name Access (hex) Bit 7 080A Ser_ScramblerB R/W 080B Ser_PRBS_Ctrl R/W 0 0820 Cfg_0_DID R 0821 Cfg_1_BID R/W* 0 0822 Cfg_3_SCR_L R/W* SCR 0823 Cfg_4_F R/W* 0 0824 Cfg_5_K R/W* 0 ...
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... NXP Semiconductors 11.6.3 Register description 11.6.3.1 ADC control registers Table 18. Register SPI control (address 0003h) Default values are highlighted. Bit Symbol Access ENABLE R Table 19. Register Reset and Power-down mode (address 0005h) Default values are highlighted. Bit Symbol Access 7 SW_RST R ...
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... NXP Semiconductors Table 21. Register Vref (address 0008h) Default values are highlighted. Bit Symbol Access INTREF_EN R INTREF[2:0] R/W Table 22. Digital offset adjustment (address 0013h) Default values are highlighted. Register offset Decimal +31 ... 0 ... −32 Table 23. Register Test pattern 1 (address 0014h) Default values are highlighted. ...
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... NXP Semiconductors Table 24. Register Test pattern 2 (address 0015h) Default values are highlighted. Bit Symbol Access TESTPAT_2[11:4] R/W Table 25. Register Test pattern 3 (address 0016h) Default values are highlighted. Bit Symbol Access TESTPAT_3[3:0] R 11.6.4 JESD204A digital control registers Table 26. SER_Status (address 0801h) Default values are highlighted ...
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... NXP Semiconductors Table 28. SER_Control1 (address 0805h) Default values are highlighted. Bit Symbol 1 REV_ENCODER 0 REV_SERIAL Table 29. SER_Analog_Ctrl (address 0808h) Default values are highlighted. Bit Symbol SWING_SEL[2:0] Table 30. SER_ScramblerA (address 0809h) Default values are highlighted. Bit Symbol LSB_INIT[6:0] Table 31 ...
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... NXP Semiconductors Table 34. Cfg_1_BID (address 0821h) Default values are highlighted. Bit Symbol BID[3:0] Table 35. Cfg_3_SCR_L (address 0822h) Default values are highlighted. Bit Symbol 7 SCR Table 36. Cfg_4_F (address 0823h) Default values are highlighted. Bit Symbol F[2:0] Table 37 ...
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... NXP Semiconductors Table 41. Cfg_9_S (address 0828h) Default values are highlighted. Bit Symbol Table 42. Cfg_10_HD_CF (address 0829h) Default values are highlighted. Bit Symbol CF[1:0] Table 43. Cfg_02_2_LID (address 082Dh) Default values are highlighted. Bit Symbol LID[4:0] Table 44 ...
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... NXP Semiconductors Table 45. Lane_0_Ctrl (address 0871h) Default values are highlighted. Bit Symbol 2 LANE_POL 1 RESERVED 0 LANE_PD Table 46. ADC_0_Ctrl (address 0891h) Default values are highlighted. Bit Symbol ADC_MODE[1: ADC_PD ADC1213S_SER Product data sheet …continued Access Value Description R/W defines lane polarity: ...
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... NXP Semiconductors 12. Package outline HVQFN32R: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; resin based; body 0.8 mm terminal 1 index area terminal 1 index area 32 Dimensions Unit max 0.90 0.28 7.1 4.05 mm nom 0.80 0.23 7.0 4.00 min 0.75 0.18 6.9 3.95 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included ...
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... NXP Semiconductors 13. Abbreviations Table 47. Acronym ADC DCS ESD IF IMD LSB LVCMOS LVPECL MSB OTR PRBS SFDR SNR SPI TX ADC1213S_SER Product data sheet Abbreviations Description Analog-to-Digital Converter Duty Cycle Stabilizer ElectroStatic Discharge Intermediate Frequency InterModulation Distortion Least Significant Bit Low-Voltage Complementary Metal-Oxide Semiconductor ...
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... NXP Semiconductors 14. Revision history Table 48. Revision history Document ID ADC1213S_SER v.1 ADC1213S_SER Product data sheet Release date Data sheet status 20110314 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 ADC1213S series Single 12-bit ADC; serial JESD204A interface ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Single 12-bit ADC; serial JESD204A interface NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . . 5 9 Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 10.2 Clock and digital output timing . . . . . . . . . . . . 10 10 ...