adc0820ccwmx National Semiconductor Corporation, adc0820ccwmx Datasheet - Page 15
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adc0820ccwmx
Manufacturer Part Number
adc0820ccwmx
Description
8-bit High Speed ?p Compatible A/d Converter With Track/hold Function
Manufacturer
National Semiconductor Corporation
Datasheet
1.ADC0820CCWMX.pdf
(23 pages)
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2.0 Analog Considerations
2.1 REFERENCE AND INPUT
The two V
define the zero to full-scale input range of the A to D con-
verter. This allows the designer to easily vary the span of the
analog input since this range will be equivalent to the voltage
difference between V
V
of the converter can be increased (i.e., if V
LSB=7.8 mV). The input/reference arrangement also facili-
tates ratiometric operation and in many cases the chip power
supply can be used for transducer power as well as the V
source.
This reference flexibility lets the input span not only be varied
but also offset from zero. The voltage at V
input level which produces a digital output of all zeroes.
Though V
affords nearly differential-input capability for most measure-
ment applications. Figure 13 shows some of the configura-
tions that are possible.
2.2 INPUT CURRENT
Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently
than in conventional devices. The A/D’s sampled-data com-
parators take varying amounts of input current depending on
which cycle the conversion is in.
External Reference 2.5V Full-Scale
REF
(V
REF
REF
IN
=V
is not itself differential, the reference design
REF
inputs of the ADC0820 are fully differential and
(+)−V
REF
IN
(+) and V
(−)) to less than 5V, the sensitivity
00550121
IN
(−). By reducing
REF
REF
FIGURE 13. Analog Input Options
(−) sets the
=2V then 1
Power Supply as Reference
REF
15
The equivalent input circuit of the ADC0820 is shown in
Figure 14. When a conversion starts (WR low, WR-RD
mode), all input switches close, connecting V
1 pF capacitors. Although the two 4-bit flash circuits are not
both in their compare cycle at the same time, V
input capacitors at once. This is because the MS flash
converter is connected to the input during its compare inter-
val and the LS flash is connected to the input during its
zeroing phase (Section 1.3). In other words, the LS ADC
uses V
The input capacitors must charge to the input voltage
through the on resistance of the analog switches (about 5 kΩ
to 10 kΩ). In addition, about 12 pF of input stray capacitance
must also be charged. For large source resistances, the
analog input can be modeled as an RC network as shown in
Figure 15. As R
capacitance to charge.
In RD mode, the input switches are closed for approximately
800 ns at the start of the conversion. In WR-RD mode, the
time that the switches are closed to allow this charging is the
time that WR is low. Since other factors force this time to be
at least 600 ns, input time constants of 100 ns can be
accommodated without special consideration. Typical total
input capacitance values of 45 pF allow R
without lengthening WR to give V
00550122
IN
as its zero-phase input.
S
increases, it will take longer for the input
Input Not Referred to GND
IN
more time to settle.
S
IN
IN
to be 1.5 kΩ
to thirty-one
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