adc0820ccwmx National Semiconductor Corporation, adc0820ccwmx Datasheet - Page 11

• Manufacturer Part Number: adc0820ccwmx
• Description: 8-bit High Speed ?p Compatible A/d Converter With Track/hold Function
• Manufacturer: National Semiconductor Corporation

1.0 Functional Description
which most closely approximates the analog input. In addi-
tion, the “sampled-data” comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC,
where the signal to be converted is an analog difference.
1.2 THE SAMPLED-DATA COMPARATOR
Each comparator in the ADC0820 consists of a CMOS in-
verter with a capacitively coupled input (Figures 6, 7 ). Ana-
log switches connect the two comparator inputs to the input
capacitor (C) and also connect the inverter’s input and out-
put. This device in effect now has one differential input pair.
A comparison requires two cycles, one for zeroing the com-
parator, and another for making the comparison.
In the first cycle, one input switch and the inverter’s feedback
switch (Figure 6 ) are closed. In this interval, C is charged to
the connected input (V1) less the inverter’s bias voltage (V
approximately 1.2V). In the second cycle (Figure 7 ), these
two switches are opened and the other (V2) input’s switch is
closed. The input capacitor now subtracts its stored voltage
from the second input and the difference is amplified by the
inverter’s open loop gain. The inverter’s input (V
and the output will go high or low depending on the sign of
V
The actual circuitry used in the ADC0820 is a simple but
important expansion of the basic comparator described
above. By adding a second capacitor and another set of
switches to the input (Figure 8 ), the scheme can be ex-
panded to make dual differential comparisons. In this circuit,
the feedback switch and one input switch on each capacitor
(Z switches) are closed in the zeroing cycle. A comparison is
then made by connecting the second input on each capacitor
and opening all of the other switches (S switches). The
change in voltage at the inverter’s input, as a result of the
change in charge on each input capacitor, will now depend
on both input signal differences.
1.3 ARCHITECTURE
In the ADC0820, one bank of 15 comparators is used in each
4-bit flash A/D converter (Figure 12 ). The MS (most signifi-
cant) flash ADC also has one additional comparator to detect
B
'−V
B
.
FIGURE 8. ADC0820 Comparator (from MS Flash ADC)
(Continued)
B
') becomes
00550114
B
,
11
input overrange. These two sets of comparators operate
alternately, with one group in its zeroing cycle while the other
is comparing.
When a typical conversion is started, the WR line is brought
low. At this instant the MS comparators go from zeroing to
• V
• V on C = V1−V
• C
• V
O
S
B
= stray input node capacitor
= inverter input bias voltage
= V
B
FIGURE 6. Sampled-Data Comparator
FIGURE 7. Sampled-Data Comparator
B
Compare Phase
Zeroing Phase
00550145
00550112
00550113
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