adc0820ccwmx National Semiconductor Corporation, adc0820ccwmx Datasheet - Page 10

• Manufacturer Part Number: adc0820ccwmx
• Description: 8-bit High Speed ?p Compatible A/d Converter With Track/hold Function
• Manufacturer: National Semiconductor Corporation

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Pin Name
1
2
3
4
5
6
7
8
V
DB0
DB1
DB2
DB3
WR
/RDY
Mode
RD
IN
Description of Pin Functions
Analog input; range =GND≤V
TRI-STATE data output — bit 0 (LSB)
TRI-STATE data output — bit 1
TRI-STATE data output — bit 2
TRI-STATE data output — bit 3
WR-RD Mode
WR: With CS low, the conversion is
started on the falling edge of WR.
Approximately 800 ns (the preset internal
time out, t
result of the conversion will be strobed
into the output latch, provided that RD
does not occur prior to this time out (see
Figures 3, 4 ).
RD Mode
RDY: This is an open drain output (no
internal pull-up device). RDY will go low
after the falling edge of CS; RDY will go
TRI-STATE when the result of the
conversion is strobed into the output latch.
It is used to simplify the interface to a
microprocessor system (see Figure 2 ).
Mode: Mode selection input — it is
internally tied to GND through a 50 µA
current source.
RD Mode: When mode is low
WR-RD Mode: When mode is high
WR-RD Mode
With CS low, the TRI-STATE data outputs
(DB0-DB7) will be activated when RD
goes low (see Figure 5 ). RD can also be
used to increase the speed of the
converter by reading data prior to the
preset internal time out (t
is done, the data result transferred to
output latch is latched after the falling
edge of the RD (see Figures 3, 4 ).
RD Mode
With CS low, the conversion will start with
RD going low, also RD will enable the
TRI-STATE data outputs at the completion
of the conversion. RDY going TRI-STATE
and INT going low indicates the
completion of the conversion (see Figure
2 ).
I
) after the WR rising edge, the
Function
I
, ∼800 ns). If this
IN
≤V
CC
10
1.0 Functional Description
1.1 GENERAL OPERATION
The ADC0820 uses two 4-bit flash A/D converters to make
an 8-bit measurement (Figure 1 ). Each flash ADC is made
up of 15 comparators which compare the unknown input to a
reference ladder to get a 4-bit result. To take a full 8-bit
reading, one flash conversion is done to provide the 4 most
significant data bits (via the MS flash ADC). Driven by the 4
MSBs, an internal DAC recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor
ladder for the A/D as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
Pin Name
9
10 GND
11 V
12 V
13 CS
14 DB4
15 DB5
16 DB6
17 DB7
18 OFL
19 NC
20 V
INT
REF
REF
CC
(−)
(+)
WR-RD Mode
INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT will go
low, ∼800 ns (the preset internal time out,
t
4 ); or INT will go low after the falling
edge of RD , if RD goes low prior to the
800 ns time out (see Figure 3). INT is
reset by the rising edge of RD or CS (see
Figures 3, 4 ).
RD Mode
INT going low indicates that the
conversion is completed and the data
result is in the output latch. INT is reset by
the rising edge of RD or CS (see Figure
2 ).
Ground
The bottom of resistor ladder, voltage
range: GND≤V
The top of resistor ladder, voltage range:
V
CS must be low in order for the RD or
WR to be recognized by the converter.
TRI-STATE data output — bit 4
TRI-STATE data output — bit 5
TRI-STATE data output — bit 6
TRI-STATE data output — bit 7 (MSB)
Overflow output — If the analog input is
higher than the V
at the end of conversion. It can be used to
cascade 2 or more devices to have more
resolution (9, 10-bit). This output is always
active and does not go into TRI-STATE as
DB0–DB7 do.
No connection
Power supply voltage
I
) after the rising edge of WR (see Figure
REF
(−)≤V
REF
(+)≤V
REF
Function
REF
(−)≤V
CC
(+), OFL will be low
(Note 5)
REF
(+) (Note 5)