adc0808s125 NXP Semiconductors, adc0808s125 Datasheet - Page 6
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adc0808s125
Manufacturer Part Number
adc0808s125
Description
Single 8-bit Adc, Up To 125 Mhz Or 250 Mhz
Manufacturer
NXP Semiconductors
Datasheet
1.ADC0808S125.pdf
(23 pages)
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NXP Semiconductors
ADC0808S125_ADC0808S250_2
Product data sheet
7.2 Digital output coding
Table 4.
The digital outputs are 1.8 V CMOS compatible.
The data output format can be either binary or 2’s complement.
Table 5.
V
The in-range CMOS output pin IR will be HIGH during normal operation. When the ADC
input reaches either positive or negative full-scale, the IR output will be LOW.
Selection between output coding is controlled by pins OTC and CE_N.
Table 6.
[1]
Pin CLKSEL
HIGH or not connected
LOW
Code
Underflow
0
1
:
127
:
254
255
Overflow
2’s complement outputs
Pin OTC
LOW
HIGH
X
i(p-p)
[1]
X = don’t care.
= 2.0 V; V
Clock input format selection
Output coding with differential inputs
Output format selection
Inputs (V)
V
< 0.45
0.45
-
:
0.95
:
-
1.45
> 1.45
i(IN)
ref(fs)
= 1.25 V; typical values to AGND.
Rev. 02 — 7 October 2008
V
> 1.45
1.45
-
:
0.95
:
-
0.45
< 0.45
i(INN)
Chip enable
Pin CE_N
LOW
LOW
HIGH
Output
Pin IR
LOW
HIGH
HIGH
:
HIGH
:
HIGH
HIGH
LOW
Single 8-bit ADC, up to 125 MHz or 250 MHz
Clock input signal
Pins CLK+ and CLK
LVDS
1.8 V CMOS
Output data
Pins D0 to D7, CCS and IR
active; binary
active; 2’s complement
high-impedance
ADC0808S125/250
Outputs D7 to D0
Binary
0000 0000
0000 0000
0000 0001
:
0111 1111
:
1111 1110
1111 1111
1111 1111
2’s complement
1000 0000
1000 0000
1000 0001
:
1111 1111
:
0111 1110
0111 1111
0111 1111
© NXP B.V. 2008. All rights reserved.
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