CY2213 Cypress Semiconductor Corp., CY2213 Datasheet - Page 5

• Manufacturer Part Number: CY2213
• Description: Lvpecl Outputs, Output Multiplier Select, OE, I2C
• Manufacturer: Cypress Semiconductor Corp.

Document #: 38-07263 Rev. *E
State Transition Characteristics
Specifies the maximum settling time of the CLK and CLKB
outputs from device power-up. For V
sequences are allowed to power-up and power-down the
CY2213.
AC Device Characteristics
V
t
t
t
t
t
t
t
t
Phase Noise
DC
t
t
BW
CYCLE
JCRMS
JCPK
JPRMS
JPPK
JLT
JLT
JLT
DC,ERR
CR
DD
, t
Parameter
LOOP
/V
From
CF
DDX
On CLK/CLKB Normal
Clock cycle time
Cycle-to-cycle RMS jitter
At 125-MHz frequency
At 400-/500-MHz frequency
Cycle-to-cycle jitter (pk-pk)
At 125-MHz frequency
At 200-MHz frequency, XF = 25 MHz
At 400-/500-MHz frequency
Period jitter RMS
At 125-MHz frequency
At 400-/500-MHz frequency
Period jitter (pk-pk)
At 125-MHz frequency
At 200-MHz frequency, XF = 25 MHz
At 400-/500-MHz frequency
Long term RMS Jitter (P < 20)
At 125-MHz frequency
At 400-/500-MHz frequency
Long term RMS Jitter (20 < P < 40)
At 125-MHz frequency
At 400-/500-MHz frequency
Long-term RMS Jitter (40 < P < 60)
At 125-MHz frequency
At 400-/500-MHz frequency
Phase Noise at 10 kHz (x8 mode) @ 125 MHz
Long-term average output duty cycle
Cycle-cycle duty cycle error at x8 with
15.625-MHz input
Output rise and fall times (measured at 20% –
80% of V
PLL Loop Bandwidth
To
OHmin
and V
Transition Latency
Description
OLmax
DD
3 ms
and V
)
DDX
Time from V
any
DD
2.50 (400 MHz)
50 kHz (–3 dB)
/V
DDX
–107
Min.
100
45
is applied and settled to CLK/CLKB outputs settled.
Description
8 MHz (–20 dB)
8.00 (125 MHz)
43.75/35
43.75/35
62.5/50
87.5/70
0.25%
6.25/5
1.75%
0.25%
6.25/5
1.75%
50/40
Max.
2.0%
2.5%
3.5%
–92
400
140
160
140
200
280
20
55
20
65
55
70
CY2213
Page 5 of 10
% t
% t
% t
% t
% t
% t
% t
Unit
dBc
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%