m41st95w STMicroelectronics, m41st95w Datasheet - Page 19

• Manufacturer Part Number: m41st95w
• Description: 5.0 Or 3.0v, 512 Bit 64 Bit X 8 Serial Rtc Spi Sram And Nvram Supervisor
• Manufacturer: STMicroelectronics

Figure 15. Back-up Mode Alarm Waveforms
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00 =
10 = 1 second, and 11 = 4 seconds. The amount
of time-out is then determined to be the multiplica-
tion of the five-bit multiplier value with the resolu-
tion. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M41ST95Y/W sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (0Fh).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0,' the watchdog will activate the IRQ/FT/OUT
pin when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for t
The Watchdog register and the AFE, ABE, SQWE,
and FT Bits will reset to a '0' at the end of a Watch-
dog time-out when the WDS Bit is set to a '1.'
REC
V CC
V PFD
V SO
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT
.
1
/
16
second, 01 =
HIGH-Z
1
/
4
second,
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
2. the microprocessor can perform a WRITE of
The time-out period then starts over. The WDI pin
should be tied to V
form a software reset of the watchdog timer, the
original time-out period can be written into the
Watchdog Register, effectively restarting the
count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT pin. This will also
disable the watchdog function until it is again pro-
grammed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT/OUT pin and the Frequency Test (FT)
function is activated, the watchdog function pre-
vails and the Frequency Test function is denied.
applied to the Watchdog Input pin (WDI), or
the Watchdog Register.
SS
M41ST95Y*, M41ST95W
if not used. In order to per-
tREC
HIGH-Z
AI03920
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