m41st85w STMicroelectronics, m41st85w Datasheet - Page 19

• Manufacturer Part Number: m41st85w
• Description: 3.0/3.3v I 2c Combination Serial Rtc, Nvram Supervisor And Microprocessor Supervisor
• Manufacturer: STMicroelectronics

3
Note:
3.1
3.2
Clock operation
The eight byte clock register (see
read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths
of Seconds, Seconds, Minutes, and Hours are contained within the first four registers.
A WRITE to any clock register will result in the Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/Hours Register) contain the CENTURY
ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle,
either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial
state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain
the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month
and Years. The ninth clock register is the Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a
'1' will cause the oscillator to stop. If the device is expected to spend a significant amount of
time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0'
the oscillator restarts within one second.
The eight Clock Registers may be read one byte at a time, or in a sequential block. The
Control Register (Address location 08h) may be accessed independently. Provision has
been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
Power-down time-stamp
When a power failure occurs, the Halt Update Bit (HT) will automatically be set to a '1.' This
will prevent the clock from updating the TIMEKEEPER
read the exact time of the power-down event. Resetting the HT Bit to a '0' will allow the clock
to update the TIMEKEEPER registers with the current time. For more information, see
Application Note AN1572.
TIMEKEEPER
The M41ST85W offers 20 internal registers which contain Clock, Alarm, Watchdog, Flag,
Square Wave and Control data. These registers are memory locations which contain
external (user accessible) and internal copies of the data (usually referred to as BiPORT
TIMEKEEPER cells). The external copies are independent of internal functions except that
they are updated periodically by the simultaneous transfer of the incremented internal copy.
The internal divider (or clock) chain will be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a Stop Condition or when
the pointer increments to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data in BCD. Control, Watchdog and Square
Wave Registers store data in Binary Format.
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registers
Table 2 on page
20) is used to both set the clock and to
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registers, and will allow the user to
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