pcf2113du/f4 NXP Semiconductors, pcf2113du/f4 Datasheet - Page 34

• Manufacturer Part Number: pcf2113du/f4
• Description: Pcf2113x Lcd Controllers/drivers
• Manufacturer: NXP Semiconductors

Philips Semiconductors
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition.
10.2.1
Before any data is transmitted on the I
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
START procedure. The I
different PCF2113x read and write cycles is shown in
Figs 24 to 26. The slow down feature of the I
protocol (receiver holds SCL LOW during internal
operations) is not used in the PCF2113x.
2001 Dec 19
handbook, full pagewidth
LCD controllers/drivers
I
2
C-
SCL
SDA
BUS PROTOCOL
TRANSMITTER/
RECEIVER
MASTER
2
C-bus configuration for the
SDA
SCL
RECEIVER
2
C-bus, the device
SLAVE
2
Fig.20 System configuration.
C-bus
data valid
data line
stable;
Fig.21 Bit transfer.
TRANSMITTER/
RECEIVER
SLAVE
34
change
allowed
of data
10.2.2
Transmitter: the device which sends the data to the bus
Receiver: the device which receives the data from the
bus
Master: the device which initiates a transfer generates
clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronization: procedure to synchronize the clock
signals of two or more devices.
D
EFINITIONS
TRANSMITTER
MASTER
MBC621
TRANSMITTER/
RECEIVER
MASTER
Product specification
PCF2113x
MGA807