pcf2113du/f4 NXP Semiconductors, pcf2113du/f4 Datasheet - Page 32

• Manufacturer Part Number: pcf2113du/f4
• Description: Pcf2113x Lcd Controllers/drivers
• Manufacturer: NXP Semiconductors

Philips Semiconductors
10 INTERFACES TO MICROCONTROLLER
10.1
The PCF2113x can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
In 8-bit mode data is transferred as 8-bit bytes using the
8 data lines DB7 to DB0. Three further control lines E,
RS and R/W are required (see Chapter 6).
In 4-bit mode data is transferred in two cycles of 4 bits
each using pins DB7 to DB4 for the transaction.
The higher order bits (corresponding to DB7 to DB4 in
8-bit mode) are sent in the first cycle and the lower order
bits (DB3 to DB0 in 8-bit mode) in the second cycle. Data
transfer is complete after two 4-bit data transfers. It should
be noted that two cycles are also required for the busy flag
check. 4-bit operation is selected by instruction, see
Figs 17 to 19 for examples of bus protocol.
In 4-bit mode, pins DB3 to DB0 must be left open-circuit.
They are pulled up to V
2001 Dec 19
LCD controllers/drivers
Parallel interface
R/W
DB7
DB6
DB5
DB4
RS
E
DD
internally.
instruction
IR7
IR6
IR5
IR4
write
IR3
IR2
IR1
IR0
Fig.17 4-bit transfer example.
AC6
AC5
AC4
BF
address counter read
busy flag and
32
10.2
The I
between different ICs or modules. The two lines are the
Serial Data line (SDA) and the Serial Clock Line (SCL).
Both lines must be connected to a positive supply via
pull-up resistors. Data transfer may be initiated only when
the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH level signal put on the bus
by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte.
Also a master receiver must generate an acknowledge
after the reception of each byte that has been clocked out
of the slave transmitter.
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration).
AC3
AC2
AC1
AC0
2
C-bus is for bidirectional, two-line communication
I
2
C-bus interface
DR7
DR6
DR5
DR4
data register
read
DR3
DR2
DR1
DR0
MGA804
Product specification
PCF2113x