74lvth322374 Fairchild Semiconductor, 74lvth322374 Datasheet - Page 2

• Manufacturer Part Number: 74lvth322374
• Description: Low Voltage 32-bit D-type Flip-flop With 3-state Outputs And 25 ?series Resistors In The Outputs Preliminary
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
Connection Diagram
Truth Tables
H
L
X
Functional Description
The LVTH322374 consists of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs.
The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be
shorted together to obtain full 32-bit operation. Each byte has a buffered clock and buffered Output Enable common to all
flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their indi-
vidual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP
Output Enable (OE
the high impedance state. Operation of the OE
LOW Voltage Level
HIGH Voltage Level
Immaterial
CP
CP




L
X
L
X
1
3
n
Inputs
OE
Inputs
OE
) LOW, the contents of the flip-flops are available at the outputs. When OE
H
H
(Top Thru View)
L
L
L
L
L
L
1
3
I
16
I
0
H
X
X
H
X
X
–I
L
–I
L
7
23
n
Outputs
Outputs
O
input does not affect the state of the flip-flops.
O
16
0
O
O
H
H
–O
L
Z
–O
L
Z
o
o
7
23
2
Pin Descriptions for FBGA
FBGA Pin Assignments
Z
O
OE
CP
I
O
o
0
–I
0
HIGH Impedance
Pin Names
–O
Previous O
n
G
M
n
A
B
C
D
E
F
H
K
L
N
P
R
T
J
31
CP
CP




31
X
X
L
L
2
4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
1
o
11
13
14
17
19
21
23
25
27
29
30
1
3
5
7
9
before HIGH-to-LOW of CP
Inputs
Inputs
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
3-STATE Outputs
OE
OE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
H
H
L
L
L
L
L
L
2
10
12
15
16
18
20
22
24
26
28
31
0
2
4
6
8
2
4
GND
V
GND
GND
V
GND
GND
V
GND
GND
V
GND
OE
OE
OE
OE
CC1
CC1
CC2
CC2
3
n
1
2
3
4
I
I
24
8
is HIGH, the outputs go to
Description
–I
H
X
X
H
X
X
L
–I
L
15
31
GND
V
GND
GND
V
GND
GND
V
GND
GND
V
GND
CP
CP
CP
CP
CC1
CC1
CC2
CC2
n
4
) transition. With the
1
2
3
4
Preliminary
I
I
I
I
I
I
I
I
I
I
I
O
Outputs
Outputs
I
I
I
I
I
O
5
10
12
15
16
18
20
22
24
26
28
31
0
2
4
6
8
24
8
O
O
–O
H
H
L
Z
–O
L
Z
o
o
15
31
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
6
11
13
14
17
19
21
23
25
27
29
30
1
3
5
7
9