74lvth322373 Fairchild Semiconductor, 74lvth322373 Datasheet - Page 2

• Manufacturer Part Number: 74lvth322373
• Description: Low Voltage 32-bit Transparent Latch With 3-state Outputs And 25 ?series Resistors In The Outputs
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
Connection Diagram
Truth Table
H
Functional Description
The LVT322373 and LVTH322373 contain thirty-two D-type latches with 3-STATE standard outputs. The device is byte con-
trolled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full
32-bit operation. The following description applies to each byte. When the Latch Enable (LE
enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input
changes. When LE
HIGH-to-LOW transition of LE
is LOW, the standard outputs are in the 2-state mode. When OE
mode but this does not interfere with entering new data into the latches.
HIGH Voltage Level
LE
LE
H
H
H
H
X
L
X
L
1
3
Inputs
OE
Inputs
OE
n
H
H
(Top Thru View)
L
L
L
L
L
L
is LOW, the latches store information that was present on the D inputs a setup time preceding the
L
1
3
LOW Voltage Level
n
. The 3-STATE standard outputs are controlled by the Output Enable (OE
I
16
I
0
X
H
X
X
H
X
–I
L
–I
L
7
23
X
Immaterial
Outputs
Outputs
O
O
16
0
O
O
H
H
–O
Z
L
–O
Z
L
0
0
7
23
Z
2
HIGH Impedance
Pin Descriptions
FBGA Pin Assignments
n
OE
LE
I
O
0
is HIGH, the standard outputs are in the high impedance
–I
0
Pin Names
n
–O
G
M
n
A
B
C
D
E
F
H
K
L
N
P
R
T
J
31
LE
LE
31
H
H
H
H
X
X
L
L
2
4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
1
11
13
14
17
19
21
23
25
27
29
30
1
3
5
7
9
O
o
Inputs
Inputs
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
3-STATE Outputs
OE
OE
Previous O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
H
H
L
L
L
L
L
L
2
10
12
15
16
18
20
22
24
26
28
31
0
2
4
6
8
2
4
n
GND
V
GND
GND
V
GND
GND
V
GND
GND
V
GND
OE
OE
OE
OE
o
) input is HIGH, data on the D
CC1
CC1
CC2
CC2
3
prior to HIGH-to-LOW transition of LE
1
2
3
4
I
I
24
8
Description
–I
X
H
X
X
H
X
L
–I
L
15
31
GND
V
GND
GND
V
GND
GND
V
GND
GND
V
GND
LE
LE
LE
LE
CC1
CC1
CC2
CC2
4
1
2
3
4
n
) input. When OE
I
I
I
I
I
I
I
I
I
I
I
O
Outputs
Outputs
I
I
I
I
I
O
5
10
12
15
16
18
20
22
24
26
28
31
0
2
4
6
8
24
8
O
O
–O
H
H
Z
L
–O
Z
L
0
0
15
31
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
6
11
13
14
17
19
21
23
25
27
29
30
1
3
5
7
9
n
n