74lvth322373 Fairchild Semiconductor, 74lvth322373 Datasheet

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74lvth322373

Manufacturer Part Number
74lvth322373
Description
Low Voltage 32-bit Transparent Latch With 3-state Outputs And 25 ?series Resistors In The Outputs
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2002 Fairchild Semiconductor Corporation
74LVT322373G
(Note 1) (Note 2)
74LVTH322373G
(Note 1) (Note 2)
74LVT322373 • 74LVTH322373
Low Voltage 32-Bit Transparent Latch
with 3-STATE Outputs
and 25 Series Resistors in the Outputs
General Description
The LVT322373 and LVTH322373 contain thirty-two non-
inverting latches with 3-STATE outputs and are intended
for bus oriented applications. The device is byte controlled.
The flip-flops appear transparent to the data when the
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the setup time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the outputs are in a high impedance state.
The LVTH322373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low voltage (3.3V) V
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT322373 and
LVTH322373 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Ordering Code:
Note 1: Ordering Code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number
Package Number
(Preliminary)
BGA96A
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
DS500742
CC
Features
Input and output interface capability to systems at
5V V
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322373),
also available without bushold feature (74LVT322373)
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs include equivalent series resistance of 25
make external termination resistors unnecessary and
reduce overshoot and undershoot
ESD performance:
Human-body model
Machine model
Charged-device model
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
CC
Package Description
200V
2000V
1000V
May 2002
Revised May 2002
www.fairchildsemi.com
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74lvth322373 Summary of contents

Page 1

... Features Input and output interface capability to systems Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH322373), also available without bushold feature (74LVT322373) Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free bus loading Outputs include equivalent series resistance of 25 ...

Page 2

Connection Diagram (Top Thru View) Truth Table Inputs – Inputs – ...

Page 3

Logic Diagrams V is associated with Bytes 1 and 2. CC1 V is associated with Bytes 3 and 4. CC2 Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Supply Current ...

Page 5

DC Electrical Characteristics Symbol Parameter I Power Supply Current (V CCZ I Increase in Power Supply Current (V CC (Note 7) Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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