nbc12430 ON Semiconductor, nbc12430 Datasheet - Page 4

• Manufacturer Part Number: nbc12430
• Description: 3.3v/5vprogrammable Pll Synthesized Clock Generator
• Manufacturer: ON Semiconductor

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explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable
of driving two series terminated 50 W transmission lines on the incident edge.
*
** When left Open, these inputs will default HIGH.
INPUTS
OUTPUTS
POWER
PIN FUNCTION DESCRIPTION
XTAL1, XTAL2
S_LOAD*
S_DATA*
S_CLOCK*
P_LOAD**
M[8:0]**
N[1:0]**
OE**
FREF_EXT*
XTAL_SEL**
F
TEST
V
PLL_V
GND
-
The following gives a brief description of the functionality of the NBC12430 and NBC12430A Inputs and Outputs. Unless
OUT
CC
Pin Name
When left Open, these inputs will default LOW.
, F
CC
OUT
Crystal Inputs
CMOS/TTL Serial Latch Input
(Internal Pulldown Resistor)
CMOS/TTL Serial Data Input
(Internal Pulldown Resistor)
CMOS/TTL Serial Clock Input
(Internal Pulldown Resistor)
CMOS/TTL Parallel Latch Input
(Internal Pullup Resistor)
CMOS/TTL PLL Loop Divider
Inputs (Internal Pullup Resistor)
CMOS/TTL Output Divider Inputs
(Internal Pullup Resistor)
CMOS/TTL Output Enable Input
(Internal Pullup Resistor)
CMOS/TTL Input
(Internal Pulldown Resistor)
CMOS/TTL Input
(Internal Pullup Resistor)
PECL Differential Outputs
PECL Output
Positive Supply for the Logic
Positive Supply for the PLL
Negative Power Supply
Exposed Pad for QFN-32 only
Function
NBC12430, NBC12430A
These pins form an oscillator when connected to an external series-resonant
crystal.
This pin loads the configuration latches with the contents of the shift registers. The
latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH-to-LOW transition of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
This pin loads the configuration latches with the contents of the parallel inputs
.The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW-to-HIGH transition of P_LOAD for proper
operation.
These pins are used to configure the PLL loop divider. They are sampled on the
LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled
on the LOW-to-HIGH transition of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the F
This pin can be used as the PLL Reference
This pin selects between the crystal and the FREF_EXT source for the PLL
reference signal. A HIGH selects the crystal input.
These differential, positive-referenced ECL signals (PECL) are the outputs of the
synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
The positive supply for the internal logic and output buffer of the chip, and is
connected to +3.3 V or +5.0 V.
This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
These pins are the negative supply for the chip and are normally all connected to
ground.
The Exposed Pad (EP) on the QFN-32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be
attached to a heat-sinking conduit. The pad is electrically connected to GND.
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4
OUT
Description
output.