pll102-109 PhaseLink Corp., pll102-109 Datasheet - Page 6

• Manufacturer Part Number: pll102-109
• Description: Programmable Zero Delay Clock Driver
• Manufacturer: PhaseLink Corp.

TABLE 3: Output Drive Strength Programming Summary:
6. Byte 9: Buffer Drive Strength Control Register
7. Byte 10: Buffer Drive Strength Control Register
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Bit<2:0>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
111
110
101
100
011
010
001
000
Strength
Strength
DDRA
DDRC
Programming Setting
-
-
-
-
-
-
Default
Name
Name
+40%
+30%
+20%
+10%
-10%
-20%
-30%
-
-
-
-
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
-
-
-
-
-
-
Setting applies to the following outputs
1. DDRA (CLK0, CLK1, CLK5)
2. DDRB (CLK2, CLK3, CLK4)
3.
FBOUT
Default
Default
Programmable DDR Zero Delay Clock Driver
1
1
0
1
1
1
1
0
1
1
-
-
-
-
-
-
Reserved.
Reserved.
These three bits will program drive strength for CLK0, CLK1 and
CLK5 output clocks (see Table 3).
Reserved
Reserved
Reserved
Reserved.
Reserved.
These three bits will program drive strength for CLK2, CLK3 and
CLK4 output clocks (see Table 3).
Reserved
Reserved
Reserved
Preliminary
Description
Description
PLL102-109
Rev 02/26/03 Page 6