pll102-109 PhaseLink Corp., pll102-109 Datasheet - Page 2

• Manufacturer Part Number: pll102-109
• Description: Programmable Zero Delay Clock Driver
• Manufacturer: PhaseLink Corp.

PIN DESCRIPTIONS
Functionality
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
2.5V (Nom)
2.5V (Nom)
ADDR_SEL
CLKC(0:5)
CLKT(0:5)
FB_OUTT
CLK_INT
FB_INT
SDATA
AVDD
Name
AGND
AVDD
SCLK
GND
GND
VDD
GND
N/C
2,4,13,17,24,26
1,5,14,16,25,27
CLK_INT
INPUTS
Number
3,12,23
6,15,28
H
H
L
L
9,21
10
11
18
19
20
22
8
7
CLK_INC
Type
PWR
PWR
PWR
PWR
OUT
OUT
OUT
I/O
IN
IN
IN
IN
-
H
H
L
L
Programmable DDR Zero Delay Clock Driver
2.5V power supply.
Ground
Analog power supply (2.5V).
Analog ground.
“True” clocks of differential pair outputs.
“Complementary” clocks of differential pair outputs.
Single-ended 3.3V tolerant input.
If ADDR_SEL=0(default) Write condition (0xD4) or a read condition (0xD5)
If ADDR_SEL=1, Write condition (0xD6) or a read condition (0xD7)
Not connected.
“True” feedback output. Dedicated for external feedback. It switches at the
same frequency as the CLK_INT.
“True” feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
Serial data input for serial interface port.
CLKT
H
H
L
L
OUTPUTS
CLKC
Description
Preliminary
H
H
L
L
FB_OUTT
PLL102-109
H
H
L
L
Rev 02/26/03 Page 2
Bypass/Off
Bypass/Off
PLL State
On
On