pll102-109 PhaseLink Corp., pll102-109 Datasheet - Page 4

• Manufacturer Part Number: pll102-109
• Description: Programmable Zero Delay Clock Driver
• Manufacturer: PhaseLink Corp.

TABLE 1: Output Signals SKEW Programming Summary:
3. BYTE 6: SKEW Register (1=Enable, 0=Disable)
4. BYTE 7: SKEW Register (1=Enable, 0=Disable)
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Bit<2:0>
111
110
101
100
011
010
001
000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Default
+400ps
+300ps
+200ps
+100ps
-100ps
-200ps
-300ps
DDR Skew Setting ( 100ps/step)
DDRA
DDRC
FBOUT-SKEWEN
Skew
Skew
DDR-SKEWEN
-
-
-
-
-
-
Name
Name
-
-
Setting applies to the following
outputs:
1. DDRA: CLK0, CLK1, CLK5
2. DDRB: CLK2, CLK3,
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
-
-
-
-
-
-
Default
Default
0
1
1
1
1
0
1
1
-
-
-
-
-
-
-
-
Programmable DDR Zero Delay Clock Driver
CLK4.
Reserved
Reserved
These three bits will adjust timing of DDRA signals (CLK0, CLK1,
CLK5) either positive or negative delay up to +400ps or –300ps
with 100ps per step. (see Table 1)
Reserved
Reserved
Reserved
1= disable, 0= enable
1= disable, 0= enable
These three bits will adjust timing of DDRC signals (CLK2, CLK3,
CLK4) either positive or negative delay up to +400ps or –300ps
with 100ps per step. (see Table 1)
Reserved
Reserved
Reserved
FBOUT Skew Setting ( 200ps/step)
Default
+800ps
+600ps
+400ps
+200ps
-200ps
-400ps
-600ps
Preliminary
Description
Description
Setting applies to the following out-
puts:
1. FB_OUTT
PLL102-109
Rev 02/26/03 Page 4